Continuous-time decision feedback equalizer

• US 20060239341A1
• Filed: 04/21/2005
• Published: 10/26/2006
• Est. Priority Date: 04/21/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Rutherford, Mark D., Marlett, Mark J.
• Granted Patent: US 7,542,508 B2
• Time in Patent Office: Days
• US Class Current: 375/233
• CPC Class Codes: H04L 2025/03356 Baseband transmission
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

A continuous-time domain Decision Feedback Equalizer (DFE) for use in a serial communication channel comprises in one embodiment a summer, a decision circuit, a capture flip-flop (FF) and an N-th order active filter. The DFE and its active filter operate in continuous time to give improved performance over a discrete-time DFE. In one embodiment involving a first-order active filter, the capture FF is outside the continuous-time negative feedback loop of the DFE and involves a differential signal amplifier. In another embodiment, the capture flip-flop is inside the DFE loop, and in a third embodiment the decision circuit comprises a comparator.

Claims

1. A decision feedback equalizer for a communications system operating in a communications channel, comprising:

a comparator decision circuit having a first branch receiving a plurality of data pulse signals output from a communications channel and having a second branch receiving negative feedback,

a decision feedback equalization circuit (DFE), said DFE receiving output from said comparator decision circuit and having a feedback loop to provide negative feedback to said comparator decision circuit, said second branch of said comparator decision circuit receiving said negative feedback relating to said DFE;

wherein,

said DFE operates in the continuous time domain.

2. The apparatus of claim 1, wherein:

said DFE has a continuous-time filter in said DFE feedback loop.

3. The apparatus of claim 2, wherein:

said DFE continuous-time filter is an active filter.

4. The apparatus of claim 3, wherein:

said DFE continuous-time active filter is an active filter selected from the group consisting of operational amplifiers having passive elements, and Switched Capacitor filters.

5. The apparatus of claim 3, wherein:

said active filter is a first-order filter.

6. The apparatus of claim 3, wherein:

said active filter is a nth-order filter.

7. The apparatus of claim 6, further comprising:

a plurality of capture flip-flops acting as delay elements, operatively connected to said DFE, said nth-order active filter having a plurality of components a0, h0(s);

a1, h1(s);

a2, h2(s);

. . . an-1, hn-1(s), and is a cascading n-th order filter having said capture flip-flops as delay elements, with the output of each said flip-flop feeding their output to the subsequent component of the filter as well as to the input to the subsequent flip flop in the-cascade.

8. The apparatus of claim 6, wherein:

said nth-order filter active filter having filter coefficients, said filter coefficients selected from the group consisting of Butterworth, Bessel, Chebyshev, Sallen Key (VCVS), or elliptic filter coefficients.

9. The apparatus of claim 1, wherein:

said comparator decision circuit comprises a summer and limiting op-amp, and further comprising a capture flip-flop operatively connected to said DFE but outside said DFE feedback loop.

10. The apparatus of claim 9, wherein:

said summer is a differential signal amplifier, and said limiting op-amp comprises a plurality of Current Mode Logic amplifiers serially connected;

said DFE comprises a programmable swing amplifier operatively connected to the output of said limiting op-amp, and a feedback filter operatively connected to the output of said programmable swing amplifier.

11. The apparatus of claim 9, further comprising:

a clock, said clock generated by a phase locked loop (PLL), said capture flip-flop gated by said clock, said PLL locked to the rate of said data pulse signals, and said capture flip-flop clock substantially independent of direct coupling with the DFE loop.

12. The apparatus of claim 1, wherein:

said comparator decision circuit comprises a summer and limiting op-amp, and further comprising a capture flip-flop operatively connected to said DFE and cascaded with and in-line to said DFE feedback loop.

13. The apparatus of claim 1, wherein:

said comparator decision circuit comprises an op-amp comparator, and further comprising a capture flip-flop operatively connected to said DFE.

14. A method for decision feedback equalization using a decision feedback equalizer in a communication system, comprising the steps of:

providing a comparator decision circuit for ascertaining whether pulses in a communication receiver pulse data bit stream are a digital ‘

1’

or ‘

0’

, wherein said pulse data bit stream is received from a communication channel having transfer function H(s), said pulse data bit stream comprising data TXDATA distorted by the communication channel;

providing negative feedback to said comparator decision circuit from a negative feedback loop in a decision feedback equalizer (DFE), said decision feedback equalizer operating in the continuous time domain and having active filters, said decision feedback equalizer having a transfer function h(s);

matching said decision feedback equalizer transfer function h(s) so that it is substantially equal to the transfer function H(s) of said communication channel.

15. The method of claim 14, further comprising the steps of:

matching said decision feedback equalizer transfer function h(s) to substantially equal the transfer function H(s) of said communication channel by programming the coefficients of said active filters, said active filters having programmable coefficients.

16. The method of claim 14, further comprising the steps of:

operatively connecting a capture flip-flop to said DFE;

said comparator decision circuit comprises a summer and limiting op-amp; and

,

situating said capture flip-flop outside said DFE negative feedback loop.

17. The method of claim 14, further comprising the steps of:

operatively connecting a capture flip-flop to said DFE;

said comparator decision circuit comprises a summer and limiting op-amp; and

,

situating said capture flip-flop operatively cascaded with in-line to said DFE negative feedback loop.

18. The method of claim 14, further comprising the steps of:

operatively connecting a capture flip-flop to said DFE;

said comparator decision circuit comprises an summing amplifier and a decision circuit, said summing amplifier and decision circuit operating according to differential signaling.

19. The method of claim 14, further comprising the steps of:

operatively connecting a capture flip-flop to said DFE, said capture flip-flop lying outside the negative feedback loop;

gating said capture flip-flop with a clock, said clock generated by a phase locked loop (PLL) locked to the rate of said communication receiver pulse data bit stream received by said comparator decision circuit;

wherein,

said capture flip-flop clock is not directly dependent on direct coupling with any clock involved with the operation of the DFE.

20. A decision feedback equalization circuit for a communications channel in a system operating for serial transmission of a transmitted signal distorted by the communications channel, the communications channel having transfer function H(s), comprising:

comparator decision circuit (CDC) means for receiving negative feedback, for comparing signals and for deciding whether pulses received from the transmitted signal distorted by the communications channel should be construed as a digital 1 or 0;

decision feedback equalization (DFE) means for providing said negative feedback to said comparator decision circuit means, said DFE means having a transfer function h(s) and operating in the continuous time domain, said DFE comprising an active filter, and said DFE active filter having means for matching said decision feedback equalizer transfer function h(s) so that transfer function h(s) is substantially equal to the transfer function H(s) of said communication channel;

means for capturing the output of said CDC means to provide a corrected received data signal as output, said received data signal representing said transmitted signal corrected for distortion through the communications channel.