Method for analyzing defect data and inspection apparatus and review system

• US 20060239536A1
• Filed: 06/22/2006
• Published: 10/26/2006
• Est. Priority Date: 04/10/2001
• Status: Abandoned Application

• Current Assignee: Hisae Shibuya, Yuji Takagi
• Original Assignee: Hisae Shibuya, Yuji Takagi
• Inventors: Takagi, Yuji, Shibuya, Hisae
• Application Number:
  US11/472,399
• Publication Number:
  US 20060239536A1
• Time in Patent Office: Days
• US Class Current: 382/149
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0006 using a design-rule based approach
• CPC Class Codes: G06T 7/001 using an image reference approach

Abstract

The distribution states of defects are analyzed on the basis of the coordinates of defects detected by an inspection apparatus to classify them into a distribution feature category, or any one of repetitive defect, congestion defect, linear distribution defect, ring/lump distribution defect and random defect. In the manufacturing process for semiconductor substrates, defect distribution states are analyzed on the basis of defect data detected by an inspection apparatus, thereby specifying the cause of defect in apparatus or process.

Claims

1. A method of analyzing defect data, comprising:

generating a wafer map using information of positions of defects detected by an inspection apparatus;

grouping defects on said wafer map based on a distribution density of said defects; and

classifying said grouped defects into one of a plurality of defect categories by calculating a degree of coincidence between said grouped defects and a plurality of geometric patterns generated in accordance with a predetermined parameter of an image region of said grouped defects.

2. A method of analyzing defect data according to claim 1, wherein said geometric patterns stored in a memory are generated by calculation.

3. A method of analyzing defect data according to claim 1, wherein said geometric patterns stored in a memory include a ring pattern and a part of the ring pattern.

4. An apparatus for analyzing defect data, comprising:

a first processor which generates a wafer map using information of positions of defects detected by an inspection apparatus;

a second processor which groups defects on said wafer map by a distribution density of said defects; and

a third processor which classifies said grouped defects into one of a plurality of defect categories by calculating a degree of coincidence between said grouped defects and a plurality of geometric patterns generated in accordance with a predetermined parameter of an image region of said grouped defects.

5. An apparatus for analyzing defect data according to claim 4, wherein said geometric patterns stored in a memory are generated by calculation in said third processor.

6. An apparatus for analyzing defect data according to claim 4, wherein said geometric patterns stored in a memory include a ring pattern and a part of the ring pattern.