Technique for manufacturing silicon structures

• US 20060240583A1
• Filed: 04/25/2005
• Published: 10/26/2006
• Est. Priority Date: 04/25/2005
• Status: Active Grant

• Current Assignee: Delphi Technologies, Inc. (BorgWarner Incorporated)
• Original Assignee: Delphi Technologies, Inc. (BorgWarner Incorporated)
• Inventors: Chilcott, Dan W., Baney, William J.
• Granted Patent: US 7,179,668 B2
• Time in Patent Office: Days
• US Class Current: 438/22
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 2203/0315 Cavities
• CPC Class Codes: B81C 1/00158 Diaphragms, membranes manufacture process for semi-permeable inorganic membranes B01D67/0039
• CPC Class Codes: B81C 2201/014 by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively

Abstract

A technique for manufacturing silicon structures includes etching a cavity into a first side of an epitaxial wafer. A thickness of an epitaxial layer is selected, based on a desired depth of the etched cavity and a desired membrane thickness. The first side of the epitaxial wafer is then bonded to a first side of a handle wafer. After thinning the epitaxial wafer until only the epitaxial layer remains, desired circuitry is formed on a second side of the remaining epitaxial layer, which is opposite the first side of the epitaxial wafer.

Claims

1. A method for manufacturing silicon structures, comprising the steps of:

etching a cavity into a first side of an epitaxial wafer, wherein a thickness of an epitaxial layer is selected based on a desired depth of the etched cavity and a desired membrane thickness;

bonding the first side of the epitaxial wafer to a first side of a handle wafer;

removing a desired portion of the epitaxial wafer to provide the epitaxial layer; and

forming desired circuitry on a second side of the epitaxial layer, wherein the second side of the epitaxial layer is opposite the first side of the epitaxial wafer.

2. The method of claim 1, wherein the handle wafer is a non-epitaxial N-type silicon wafer.

3. The method of claim 1, further comprising the step of:

forming a first oxide layer on outer surfaces of the epitaxial wafer; and

masking portions of the first oxide layer on the first side of the epitaxial wafer in a desired pattern, wherein the cavity is etched into the first side of the epitaxial wafer through an unmasked portion of the first oxide layer.

4. The method of claim 2, further comprising the step of:

removing the first oxide layer from the outer surfaces of the epitaxial wafer; and

forming a second oxide layer on the exposed silicon surfaces of the epitaxial wafer, before bonding the first side of the epitaxial wafer to the first side of the handle wafer.

5. The method of claim 3, further comprising the step of:

removing the second oxide layer from the second side of the epitaxial wafer.

6. The method of claim 1, wherein the epitaxial wafer is an N-type silicon wafer.

7. The method of claim 1, wherein the handle wafer is at least one of a P-type++ silicon wafer and a silicon wafer having a (111) Miller Indices.

8. The method of claim 4, further comprising the step of:

forming a hole through the handle wafer from a second side of the handle wafer to the first side of the handle wafer approximate the cavity in the epitaxial wafer, wherein the second oxide layer on the second side of the epitaxial wafer functions as an etch stop layer.

9. The method of claim 8, wherein the hole is formed using either wet or dry etch processing.

11. The method of claim 9, further comprising the step of:

forming a first oxide layer on outer surfaces of the epitaxial wafer; and

masking portions of the first oxide layer on the first side of the epitaxial wafer in a desired pattern, wherein the cavity is etched into the first side of the epitaxial wafer through an unmasked portion of the first oxide layer.

13. The method of claim 11, further comprising the step of:

removing the second oxide layer from the second side of the epitaxial wafer.

14. The method of claim 9, wherein the epitaxial wafer is an N-type silicon wafer and the buried etch stop layer is a P-type++ layer.

15. The method of claim 9, wherein the handle wafer is at least one of a P-type++ silicon wafer and a silicon wafer having a (111) Miller Indices.

10. A method for manufacturing silicon structures, comprising the steps of:

providing an epitaxial wafer including a buried etch stop layer positioned at a desired depth in the epitaxial wafer;

etching a cavity into a first side of the epitaxial wafer, wherein a thickness of an epitaxial layer is selected based on a desired depth of the etched cavity and a membrane thickness, and wherein the membrane thickness is the difference between the location of the buried etch stop layer and the depth of the etched cavity;

bonding the first side of the epitaxial wafer to a first side of a handle wafer;

removing a portion of the epitaxial wafer from a second side of the epitaxial wafer until the buried etch stop layer is exposed, wherein the second side of the epitaxial wafer is opposite the first side of the epitaxial wafer;

removing the etch stop layer from the epitaxial layer; and

forming desired circuitry on the second side of the epitaxial layer.

12. The method of claim 10, further comprising the step of:

removing the first oxide layer from the outer surfaces of the epitaxial wafer; and

forming a second oxide layer on the outer surfaces of the epitaxial wafer, before bonding the first side of the epitaxial wafer to the first side of the handle wafer.

16. The method of claim 12, further comprising the step of:

forming a hole through the handle wafer from a second side of the handle wafer to the first side of the handle wafer approximate the cavity in the epitaxial wafer, wherein the second oxide layer on the first side of the epitaxial wafer functions as an etch stop layer.

17. The method of claim 16, wherein the hole is formed using either wet or dry etch processing.

19. The method of claim 17, further comprising the step of:

forming a first oxide layer on outer surfaces of the epitaxial wafer; and

masking portions of the first oxide layer on the first side of the epitaxial wafer in a desired pattern, wherein the cavity is etched into the first side of the epitaxial wafer through an unmasked portion of the first oxide layer.

21. The method of claim 19, further comprising the step of:

removing the second oxide layer from the second side of the epitaxial wafer.

18. A method for manufacturing silicon structures, comprising the steps of:

etching a cavity into a first side of an epitaxial wafer, wherein a thickness of the epitaxial layer is selected based on a desired depth of the etched cavity and a desired membrane thickness;

bonding the first side of the epitaxial wafer to a first side of a handle wafer;

thinning the epitaxial wafer until only an epitaxial layer remains; and

forming desired circuitry on a second side of the epitaxial layer, wherein the second side of the epitaxial layer is opposite the first side of the epitaxial wafer, and wherein the epitaxial layer is an N-type silicon layer and the buried etch stop layer is a P-type++ layer, where the handle wafer is at least one of a P-type++ silicon wafer or a silicon wafer having a (111) Miller Indices.

20. The method of claim 18, further comprising the step of:

removing the first oxide layer from the outer surfaces of the epitaxial wafer; and

forming a second oxide layer on the outer surfaces of the epitaxial wafer, before bonding the first side of the epitaxial wafer to the first side of the handle wafer.