DRAM access transistor and method of formation
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Abstract
Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Polysilicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.
67 Citations
122 Claims
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1-99. -99. (canceled)
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100. A self-aligned recessed gate structure, comprising:
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a first recessed gate region having a first width, said first recessed gate region being located below a surface of a semiconductor substrate;
a second gate region having a second width, said second gate region extending above said surface of said semiconductor substrate, wherein said second gate region comprises a gate layer, a conductive layer, and an insulating layer;
an oxide layer located on sidewalls and bottom of each of said gate layer and said first recessed gate region; and
insulating spacers located on sidewalls of said second gate region but not on said sidewalls of said first recessed gate region, wherein said insulating spacers are in contact with said insulating layer, said conductive layer and said oxide layer located on said sidewalls of said gate layer. - View Dependent Claims (101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111)
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112. A memory cell, comprising:
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a silicon substrate;
a transistor including a self-aligned recessed gate structure fabricated within said silicon substrate;
a doped region in said silicon substrate disposed adjacent to said gate structure; and
a capacitor formed over and electrically connected with said doped region, wherein said self-aligned recessed gate structure further comprises;
a first recessed gate region having a first width located below a surface of said silicon substrate;
a second gate region having a second width greater than said first width, said second gate region extending above said surface of said semiconductor substrate, wherein said second gate region further comprises a gate layer, a conductive layer, and an insulating layer; and
an oxide layer located on sidewalls and bottom of each of said gate layer and said first recessed gate region. - View Dependent Claims (113, 114, 115, 116, 117, 118, 119, 120, 121, 122)
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Specification