DC offset cancellation circuits and methods

• US 20060240779A1
• Filed: 04/22/2005
• Published: 10/26/2006
• Est. Priority Date: 04/22/2005
• Status: Active Grant

• Current Assignee: Cobblestone Wireless, LLC (Bedrock IP Co., Ltd.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Mehrnia, Alireza, Bagheri, Rahim, Djafari, Masoud, Rostami, Edris
• Granted Patent: US 7,477,885 B2
• Time in Patent Office: Days
• US Class Current: 455/63.100
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

Embodiments of the present invention include circuits and methods for reducing DC Offset. In one embodiment the present invention includes storing DC offset on internal capacitances. In one embodiment, parallel stages are used to remove DC offset corresponding to different local oscillator frequencies. Embodiments of the invention further include changing the low cutoff frequency of the DC cancellation circuits for fast calibration. In a first state, a high pass filter may have a first low cutoff frequency, and in a second state the high pass filter may have a second cutoff frequency lower than the first low cutoff frequency. The present invention also includes a variable gain amplifier with reduced DC offset.

Claims

1. A wireless receiver comprising:

a mixer having a first input, a second input and an output, wherein the first input is coupled to a first amplifier to receive an amplified RF signal and the second input is coupled to a frequency synthesizer to receive a first signal having one of a plurality of frequencies; and

a plurality of parallel DC offset cancellation stages selectively coupled to the mixer output,

wherein if the first signal has a first frequency, then a first one of the plurality of parallel DC offset cancellation stages is coupled to the mixer output, and if the first signal has a second frequency, then a second one of the plurality of parallel DC offset cancellation stages is coupled to the mixer output.

2. The wireless receiver of claim 1 wherein, in a first state, at least one of the DC offset cancellation stages has a first low cutoff frequency and, in a second state, the at least one DC offset cancellation stage has a second low cutoff frequency less than the first low cutoff frequency.

3. The wireless receiver of claim 2 wherein each of the plurality of stages is coupled to a first resistance in the first state, and each of the plurality of stages is coupled to a second resistance greater than the first resistance in the second state.

4. The wireless receiver of claim 1 wherein each of the plurality of DC offset cancellation stages includes a switch and a capacitor.

5. The wireless receiver of claim 1 wherein each of the plurality of DC offset cancellation stages includes a first resistor coupled to a reference voltage through a switch.

6. The wireless receiver of claim 1 wherein each of the plurality of DC offset cancellation stages includes a variable attenuator.

7. The wireless receiver of claim 1 further comprising:

a second amplifier having an input coupled to an output of each of the plurality of parallel DC offset cancellation stages; and

a third DC offset cancellation stage coupled to an output of the second amplifier,

wherein, in a first state, the third DC offset cancellation stage has a first low cutoff frequency and, in a second state, the third DC offset cancellation stage has a second low cutoff frequency less than the first low cutoff frequency.

8. The wireless receiver of claim 7 further comprising a fourth DC offset cancellation stage coupled in parallel with the third DC offset cancellation stage.

9. The wireless receiver of claim 7 further comprising a variable attenuator coupled to an output of the third DC offset cancellation stage.

10. The wireless receiver of claim 1 wherein the DC offset cancellation stages comprise high pass filters.

11. A wireless receiver comprising a first DC offset cancellation circuit, wherein in a first state, the first DC offset cancellation circuit has a first low cutoff frequency, and in a second state, the first DC offset cancellation circuit has a second low cutoff frequency less than the first low cutoff frequency.

12. The wireless receiver of claim 11 wherein the first DC offset cancellation circuit is coupled between a mixer and a variable gain amplifier.

13. The wireless receiver of claim 12 wherein the variable gain amplifier includes at least one second DC offset cancellation circuit, wherein in the first state, the second DC offset cancellation circuit has a third low cutoff frequency greater than the first low cutoff frequency of the first DC offset cancellation circuit, and in the second state, the second DC offset cancellation circuit has a fourth low cutoff frequency less than the third low cutoff frequency.

14. The wireless receiver of claim 11 further comprising a variable gain amplifier comprising a fixed gain amplifier and variable attenuator, wherein the first DC cancellation circuits is coupled between the fixed gain amplifier and the variable attenuator.

15. The wireless receiver of claim 14 wherein the first DC cancellation circuit includes a first and second parallel DC cancellation stages.

16. A wireless receiver including a DC offset cancellation circuit, the DC offset cancellation circuit comprising:

a capacitor having a first terminal coupled to receive an input signal and a second terminal;

a first MOS transistor having a first terminal and a second terminal, the first terminal of the MOS transistor being coupled to the second terminal of the capacitor; and

a resistance coupled between the second terminal of the first MOS transistor and a reference voltage,

wherein, in a first state, the resistance has a first value so that the circuit has a first low cutoff frequency, and in a second state, the resistance has a second value so that the circuit has a second low cutoff frequency less than the first low cutoff frequency.

17. The wireless receiver of claim 16 wherein the resistance comprises a first resistor coupled to the second terminal of the first MOS transistor and a second resistor selectively coupled in parallel with the first resistor.

18. The wireless receiver of claim 16 further comprising a second MOS transistor having a source and drain coupled to the second terminal of the first MOS transistor.

19. The wireless receiver of claim 16 wherein the DC offset cancellation circuit is a differential circuit.

20. The wireless receiver of claim 16 wherein the resistance is a variable attenuator.