Apparatus and methods for control of sleep modes in a transceiver

• US 20060240798A1
• Filed: 03/10/2006
• Published: 10/26/2006
• Est. Priority Date: 03/11/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Wang, Michael Mao, Jarosinski, Tadeusz, Ganapathy, Chinnappa K.
• Granted Patent: US 8,509,859 B2
• Time in Patent Office: Days
• US Class Current: 455/343.100
• CPC Class Codes: H04B 1/1615 Switching on; Switching off, e.g. remotely battery saving circuits associated with selective call operation H04W52/00; details of power consumption reduction in a PLL, H03L7/0802, H03L7/14, H03L2207/08, H03L2207/18; muting amplifiers by gain control see H03G3/34
• CPC Class Codes: H04W 52/0225 using monitoring of external events, e.g. the presence of a signal
• CPC Class Codes: H04W 52/0293 having a sub-controller with a low clock frequency switching on and off a main controller with a high clock frequency
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Disclosed are apparatus and methods for control of sleep modes in a transceiver or receiver. In particular, a transceiver is disclosed including a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver. The transceiver also includes a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.

Claims

1. A wireless transceiver comprising:

a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver; and

a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.

2. The transceiver as defined in claim 1, wherein the sleep control logic is further configured to effect powering up of the at least a portion of the components independently and synchronously with a transceiver system timing.

3. The transceiver as defined in claim 1, wherein the sleep control logic is further configured to shut down a partial number of components of the at least a portion of the components when a portion of signal processing of a received communication signal by the transceiver has been completed prior to a predetermined timing point and shut down another portion of components of the at least a portion of the components if signal processing by the processor is completed by predetermined time.

4. The transceiver as defined in claim 1, wherein the sleep control logic is further configured to issue an interrupt signal to the processor configured to wake up the processor after determination of an end of a sleep mode by the sleep control logic.

5. The transceiver as defined in claim 1, wherein the processor is configured to program the sleep control logic with the information sent to the sleep control logic.

6. The transceiver as defined in claim 1, wherein the sleep control logic is part of baseband receiver configured to receive burst communication signals.

7. The transceiver as defined in claim 1, wherein the sleep control logic is configured to determine an end timing of a sleep mode and initiate wakeup of at least a portion of components in the transceiver.

8. The transceiver as defined in claim 7, wherein the sleep control logic is configured to issue a wakeup interrupt signal to the processor after determining an end timing of a sleep mode.

9. The transceiver as defined in claim 1, wherein the wakeup interrupt signal is a dynamic parameter determined by the processor after each received burst of data.

10. A sleep controller for use in a wireless transceiver, the controller comprising:

a sleep control logic communicatively coupled to a processor to receive information concerning sleep periods from the processor and configured to effect shutting down and powering up of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.

11. The sleep controller as defined in claim 10, wherein the sleep control logic is further configured to effect shutting down and powering up of the at least a portion of the components independently and synchronously with a transceiver system timing.

12. The sleep controller as defined in claim 10, wherein the sleep control logic is further configured to shut down a partial number of components of the at least a portion of the components when a portion of signal processing of a received communication signal by the transceiver has been completed prior to a predetermined timing point and shut down another portion of components of the at least a portion of the components if signal processing by the processor is completed by predetermined time.

13. The sleep controller as defined in claim 10, wherein the sleep control logic is further configured to issue an interrupt signal to the processor configure to wake up the processor after determination of an end of a sleep mode.

14. The sleep controller as defined in claim 10, wherein the processor is configured to program the sleep control logic with the information sent to the sleep control logic.

15. The sleep controller as defined in claim 10, wherein the sleep control logic is part of baseband receiver configured to receive burst communication signals.

16. The sleep controller as defined in claim 10, wherein the sleep control logic is configured to determine an end timing of a sleep mode and initiate wakeup of at least a portion of components in the transceiver.

17. The sleep controller as defined in claim 16, wherein the sleep control logic is configured to issue a wakeup interrupt signal to the processor after determining an end timing of a sleep mode.

18. The sleep controller as defined in claim 10, wherein the wakeup interrupt signal is a dynamic parameter determined by the processor after each received burst of data.

19. A method for controlling sleep modes in a wireless transceiver comprising:

determining timing information concerning sleep periods for at least a portion of components within the transceiver with a processor;

receiving information concerning sleep periods from the processor with a sleep control logic coupled to the processor; and

shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of and synchronous with a transceiver system timing.

20. The method as defined in claim 19, wherein the sleep control logic is further configured to shut down a partial number of components of the at least a portion of the components when a portion of signal processing of a received communication signal by the transceiver has been completed prior to a predetermined timing point and shut down another portion of components of the at least a portion of the components if signal processing by the processor is completed by predetermined time.

21. The method as defined in claim 19, further comprising:

determining an end of a sleep mode with the sleep control logic; and

issuing an interrupt signal to the processor with the sleep control logic is to wake up the processor based on the determination of the end of the sleep mode.

22. The method as defined in claim 20, wherein the processor is configured to program the sleep control logic with the information sent to the sleep control logic.

23. The method as defined in claim 19, wherein the sleep control logic is part of baseband receiver configured to receive burst communication signals.

24. The method as defined in claim 19, wherein the sleep control logic is configured to determine an end timing of a sleep mode and initiate wakeup of at least a portion of components in the transceiver.

25. The method as defined in claim 24, wherein the sleep control logic is configured to issue a wakeup interrupt signal to the processor after determining an end timing of a sleep mode.

26. The method as defined in claim 19, wherein the wakeup interrupt signal is a dynamic parameter determined by the processor after each received burst of data.

27. A transceiver apparatus comprising:

means for determining timing information concerning sleep periods for at least a portion of components within the transceiver;

means for outputting information concerning sleep periods from the means for determining and

means for executing sleep periods configured to shut down the at least a portion of the components of the transceiver during power reduction periods independent of and synchronous with the means for determining timing information.

28. The transceiver apparatus as defined in claim 27, wherein the means for executing sleep periods is further configured to shut down a partial number of components of the at least a portion of the components when part of processing of a received communication signal by the means for determining has been completed prior and to shut down another portion of components of the at least a portion of the components if signal processing by the processor is completed by predetermined time.

29. The transceiver apparatus as defined in claim 27, wherein the means for executing sleep periods is configured to determine an end of a sleep mode and issue an interrupt signal to the processor with the sleep control logic is to wake up the processor based on the determination of the end of the sleep mode.

30. The transceiver apparatus as defined in claim 29, wherein the processor is configured to program the sleep control logic with the information sent to the sleep control logic.

31. The transceiver apparatus as defined in claim 27, wherein the sleep control logic is part of baseband receiver configured to receive burst communication signals.

32. The transceiver apparatus as defined in claim 27, wherein the sleep control logic is configured to determine an end timing of a sleep mode and initiate wakeup of at least a portion of components in the transceiver.

33. The transceiver apparatus as defined in claim 32, wherein the sleep control logic is configured to issue a wakeup interrupt signal to the processor after determining an end timing of a sleep mode.

34. The transceiver apparatus as defined in claim 27, wherein the wakeup interrupt signal is a dynamic parameter determined by the processor after each received burst of data.

35. Computer-readable medium encoded with a set of instructions, the instructions comprising:

an instruction for determining timing information concerning sleep periods for at least a portion of components within the transceiver with a processor;

an instruction for receiving information concerning sleep periods from the processor with a sleep control logic coupled to the processor; and

an instruction for shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of and synchronous with a transceiver system timing.