Scalable routing and addressing

• US 20060242333A1
• Filed: 12/01/2005
• Published: 10/26/2006
• Est. Priority Date: 04/22/2005
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Torudbakken, Ola, Johnsen, Bjorn Dag
• Granted Patent: US 7,565,463 B2
• Time in Patent Office: Days
• US Class Current: 710/30
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/566 Routing instructions carried by the data packet, e.g. active networks

Abstract

PCI Express transactions can be transmitted via a shared PCI Express infrastructure. At an infrastructure ingress point an additional header comprising at least a source identifier and a target identifier is generated for a transaction packet that comprises a header portion, a data portion and an end-to-end CRC portion. The transaction packet is then transmitted with the additional header from the ingress point to an egress point. At the egress point the additional header is removed. The additional header can further include a resource key. It can further include protection information such as a CRC.

Claims

1. A method of routing transactions via a shared infrastructure, the method comprising:

at a first infrastructure point, generating an additional header comprising at least a source identifier and a target identifier for a transaction packet that comprises a header portion, a data portion and an end-to-end CRC portion;

routing the transaction packet with the additional header from the ingress point to a second point; and

at the second point, removing the additional header.

2. The method of claim 1, wherein the additional header further includes at least one of:

a resource key; and

protection information.

3. The method of claim 2, wherein the additional header includes a resource key that identifies access rights for a target resource.

4. The method of claim 2, wherein the additional header includes protection information in the form of a CRC.

5. The method of claim 1, wherein the additional header is generated as a packet separate from the transaction packet with which it is associated and is transmitted separately from that transaction packet.

6. The method of claim 5, wherein the additional header packet associated with a transaction packet is transmitted immediately prior to that transaction packet.

7. The method of claim 6, wherein a port in the infrastructure is operable, on receipt of an additional header packet, to expect a transaction packet associated therewith as a next packet to be received.

8. The method of claim 1, wherein the source identifier for a transaction packet is generated as a mapping of a requestor ID of the header portion of the transaction packet.

9. The method of claim 1, wherein the target identifier for a transaction packet is generated as a mapping of the content of an address field of the header portion of the transaction packet.

10. The method of claim 1, wherein the first infrastructure point is an ingress port of an interconnect apparatus.

11. The method of claim 10, wherein the interconnect apparatus is a switch.

12. The method of claim 1, wherein the first infrastructure point is a root complex.

13. The method of claim 1, wherein the shared infrastructure is a shared PCI Express infrastructure and the transaction packet is a transaction layer packet.

14. An interconnect apparatus for a shared infrastructure, the interconnect apparatus comprising an additional header generator, the additional header generator being operable to receive a transaction packet including a header portion, a data portion and an end-to-end CRC portion, the additional header generator being further operable to generate an additional header for the transaction packet, which additional header comprises at least a source identifier and a target identifier.

15. The interconnect apparatus of claim 14, wherein the additional header generator is operable to generate an additional header as a packet separate from the transaction packet with which it is associated, and wherein the additional header packet is transmitted separately from the transaction packet.

16. The interconnect apparatus of claim 15, wherein the additional header packet associated with a transaction packet is for transmission immediately prior to that transaction packet.

17. The interconnect apparatus of claim 14, wherein the additional header generator is operable to generate an additional header as a packet that carries the transaction packet.

18. The interconnect apparatus of claim 14, comprising an ingress port, the additional header generator forming part of the ingress port.

19. The interconnect apparatus of claim 14 in the form of a switch.

20. The interconnect apparatus of claim 14 for supporting a shared PCI Express infrastructure.

21. A computer system comprising, at an infrastructure ingress point, an additional header generator, the additional header generator being operable to receive a transaction packet including a header portion, a data portion and an end-to-end CRC portion, the additional header generator being further operable to generate an additional header for the transaction packet, which additional header comprises at least a source identifier and a target identifier.