Job level control of simultaneous multi-threading functionality in a processor

• US 20060242389A1
• Filed: 04/21/2005
• Published: 10/26/2006
• Est. Priority Date: 04/21/2005
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Browning, Luke Matthew, Mathews, Thomas Stanley
• Application Number:
  US11/111,556
• Publication Number:
  US 20060242389A1
• Time in Patent Office: Days
• US Class Current: 712/229
• CPC Class Codes: G06F 2209/507 Low-level
• CPC Class Codes: G06F 9/5044 considering hardware capabilities
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455

Abstract

Using resource sets for job-level control of the simultaneous multi-threading capability (SMT) of a processor in a data processing system. A resource set defined with respect to the processor is adapted to control whether the simultaneous multi-threading capability is enabled.

Claims

1. A data processing system comprising:

a bus;

a memory operably connected to the bus;

a processor operably connected to the bus, said processor having a simultaneous multi-threading capability; and

a resource set defined with respect to the processor, said resource set adapted to control whether the simultaneous multi-threading capability is enabled.

2. The data processing system of claim 1, wherein the resource set is an exclusive resource set.

3. The data processing system of claim 1, wherein the resource set is defined by instructions contained in a job executed on the processor.

4. The data processing system of claim 1, wherein the resource set controls whether the simultaneous multi-threading capability is enabled by controlling a state of logical processors associated with the processor.

5. The data processing system of claim 4, wherein the state is selected from the group consisting of an exclusive state and a non-exclusive state.

6. The data processing system of claim 1, wherein the processor comprises a first logical processor and a second logical processor, wherein the second logical processor is made idle using the resource set, and wherein the first logical processor and the second logical processor are associated with hardware threads on the same physical processor.

7. The data processing system of claim 6, further comprising:

a hypervisor, said hypervisor adapted to convert processors associated with the first and second logical processors into single thread operation mode.

8. A method of controlling whether a simultaneous multi-threading capability of a processor in a data processing system is enabled, said method comprising:

establishing a resource set within the data processing system;

wherein the resource set is adapted to control whether the simultaneous multi-threading capability is enabled.

9. The method of claim 8, wherein the resource set is an exclusive resource set.

10. The method of claim 8, wherein the resource set is defined by instructions contained in a job executed on the processor.

11. The method of claim 8, wherein the resource set controls whether the simultaneous multi-threading capability is enabled by controlling a state of logical processors associated with the processor.

12. The method of claim 11, wherein the state is selected from the group consisting of an exclusive state and a non-exclusive state.

13. The method of claim 8, wherein the processor comprises a first logical processor and a second logical processor, wherein the second logical processor is made idle using the resource set, and wherein the first logical processor and the second logical processor are associated with hardware threads on the same physical processor.

14. The method of claim 13, wherein in the method the data processing system further comprises a hypervisor, said hypervisor adapted to convert processors associated with the first and second logical processors into single thread operation mode.

15. A computer program product in a computer readable medium, said computer program product adapted to control whether a simultaneous multi-threading capability of a processor in a data processing system is enabled, said computer program product adapted to carry out the steps of:

establishing a resource set within the data processing system;

wherein the resource set is adapted to control whether the simultaneous multi-threading capability is enabled.

16. The computer program product of claim 15, wherein the resource set is an exclusive resource set.

17. The computer program product of claim 15, wherein the resource set is defined by instructions contained in a job executed on the processor.

18. The computer program product of claim 15, wherein the resource set controls whether the simultaneous multi-threading capability is enabled by controlling a state of logical processors associated with the processor.

19. The computer program product of claim 18, wherein the state is selected from the group consisting of an exclusive state and a non-exclusive state.

20. The computer program product of claim 15, wherein the processor comprises a first logical processor and a second logical processor, wherein the second logical processor is made idle using the resource set, and wherein the first logical processor and the second logical processor are associated with hardware threads on the same physical processor.