Software-hardware welding system

• US 20060242469A1
• Filed: 06/22/2006
• Published: 10/26/2006
• Est. Priority Date: 05/16/2000
• Status: Active Grant

• Current Assignee: Phillip M. Adams & Associates, LLC
• Original Assignee: Phillip M. Adams & Associates, LLC
• Inventors: Adams, Phillip M.
• Granted Patent: US 7,409,601 B2
• Time in Patent Office: Days
• US Class Current: 714/42
• CPC Class Codes: G01R 31/317 Testing of digital circuits
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

A system and method for a software override capability for enforcing a predetermined state for an otherwise hardware-programmable device. Software that may think it knows what it is doing may try to control a hardware device, but may not know about a hardware issue, such as another feature or defect requiring that the device stay in a certain state. The technique programmatically maintains a persistent hardware state independent of any other control software. To other software, the software layer of the invention is indistinguishable and inseparable from hardware. Nothing can slip in between. Any insertion attempt will be detected and disallowed. Features of the processor or system chips actually weld the software to the hardware, which feature disallows any software intervention between the welded software layer and the hardware.

Claims

1-20. -20. (canceled)

21. An apparatus comprising:

a defective I/O controller comprising a data buffer having at least one storage element, the defective I/O controller being configured to allow a write operation to the data buffer and a read operation from the data buffer, the read operation reading data written to the data buffer by the write operation; and

a function module to correct the defective I/O controller by assuring that the write operation has completed prior to allowing the read operation.

22. The apparatus of claim 21, wherein the function module is implemented by at least one of hardware, software, firmware, and combinations thereof.

23. The apparatus of claim 21, wherein the data buffer is a FIFO.

24. The apparatus of claim 21, wherein the defective I/O controller is a floppy diskette controller.

25. The apparatus of claim 21, further comprising a welding module to inseparably connect the function module to the defective I/O controller.

26. The apparatus of claim 21, further comprising a defense module to resist attempts by software to unweld the function module from the defective I/O controller.

27. The apparatus of claim 22, wherein the data buffer is a FIFO.

28. The apparatus of claim 27, wherein the I/O controller is a floppy diskette controller.

29. The apparatus of claim 28, further comprising a welding module to inseparably connect the function module to the defective I/O controller.

30. The apparatus of claim 29, further comprising a defense module to resist attempts by software to unweld the function module from the defective I/O controller.

31. An apparatus comprising:

a defective I/O controller comprising a data buffer having at least one storage element, the defective I/O controller being configured to allow a read operation from the data buffer and a write operation to the data buffer, the write operation writing over data read by the read operation;

a function module to correct the defective I/O controller by assuring that the read operation has completed prior to allowing the write operation;

32. The apparatus of claim 31, wherein the function module is implemented by at least one of hardware, software, firmware, and combinations thereof.

33. The apparatus of claim 31, wherein the data buffer is a FIFO.

34. The apparatus of claim 31, wherein the defective I/O controller is a floppy diskette controller.

35. The apparatus of claim 31, further comprising a welding module to inseparably connect the function module to the defective I/O controller.

36. The apparatus of claim 31, further comprising a defense module to resist attempts by software to unweld the function module from the defective I/O controller.

37. The apparatus of claim 32, wherein the data buffer is a FIFO.

38. The apparatus of claim 37, wherein the I/O controller is a floppy diskette controller.

39. The apparatus of claim 38, further comprising a welding module to inseparably connect the function module to the defective I/O controller.

40. The apparatus of claim 39, further comprising a defense module to resist attempts by software to unweld the function module from the defective I/O controller.