Error detection in a logic device without performance impact

• US 20060242537A1
• Filed: 03/30/2005
• Published: 10/26/2006
• Est. Priority Date: 03/30/2005
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Dang, Lich Xuan
• Application Number:
  US11/093,358
• Publication Number:
  US 20060242537A1
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

An apparatus and method to perform error detection in a logic device without performance impact. The apparatus includes an Error Detection Device (EDD) coupled to a memory module and a processor. The memory module connects to the processor. As information transfers from the memory module to the processor, the EDD receives the same information and checks the information for errors. The information may be instructions, data, or control sequences. If the EDD does not detect any errors in the information, the processor is allowed to complete execution of the information. If the EDD detects an error in the information transferred from the memory module, an action is sent to the processor before the erroneous information is executed. Because the error checking is done by the EDD at the same time as the transfer of information from the memory module to the processor, the performance of the system is not impacted.

Claims

1. A method of detecting errors in a device, comprising:

transmitting information from a memory module to an Error Detection Device (EDD);

transmitting the information from the memory module to a processor at the same time; and

allowing the processor to begin execution of the information, wherein the EDD checks the information for errors as the processor begins execution of the information.

2. The method of claim 1, wherein the EDD uses Hamming codes to check the information for errors

3. The method of claim 2, wherein the EDD uses a parity check to check the information for errors.

4. The method of claim 1, wherein the EDD does not reduce performance of the device.

5. The method of claim 1, further comprising sending a memory corruption action to the processor if the EDD detects an error.

6. The method of claim 5, wherein the processor completes execution of the information if the EDD detects no errors.

7. The method of claim 5, wherein the processor executes a memory corruption routine when the processor receives the memory corruption action.

8. The method of claim 7, wherein the memory corruption routine comprises at least one of activating an indicator signal, switching to a secondary system, halting the system, and beginning an error correction process.

9. The method of claim 1, further comprising stopping the processor from executing the information if the EDD detects an error in the information.

10. The method of claim 1, further comprising storing the information and an address of the information if the EDD detects an error.

11. An apparatus to detect errors in a device, comprising:

a processor;

a memory module coupled to the processor; and

an Error Detection Device (EDD) coupled to the memory module and the processor, wherein said memory module sends similar information to said EDD and said processor at the same time.

12. The apparatus of claim 11, wherein the EDD uses Hamming codes to determine if the information from the memory module has errors.

13. The apparatus of claim 12, wherein the EDD uses a parity check to determine if the information from the memory module has errors.

14. The apparatus of claim 13, wherein the EDD comprises a memory storage for storing information and an address of the information if the information has errors.

15. The apparatus of claim 11, wherein the information is data, instructions, or control sequences.

16. The apparatus of claim 11, wherein the EDD couples to the processor through interrupt, reset, and abort means.

17. The apparatus of claim 11, wherein the memory module comprises:

a memory interface, wherein said memory interface couples to the processor;

a memory device coupled to the memory interface; and

a parity module coupled to the memory interface.

18. The apparatus of claim 17, wherein said memory device couples to the EDD, wherein said parity module couples to the EDD.

19. The apparatus of claim 11, further comprising:

an Input/Output (I/O) Unit coupled to the processor; and

a peripheral module coupled to the I/O unit, wherein the I/O unit couples to the EDD.

20. The apparatus of claim 19, wherein the peripheral module comprises:

an engine control unit coupled to the I/O unit;

an automatic transmission control unit coupled to the I/O unit; and

an anti-lock brake system control unit coupled to the I/O unit.

21. The apparatus of claim 19, wherein the peripheral module comprises:

a tire pressure sensor coupled to the I/O unit;

an air intake sensor coupled to the I/O unit; and

a revolution sensor coupled to the I/O unit.

22. The apparatus of claim 19, wherein the peripheral module comprises:

a hydraulic actuator coupled to the I/O unit;

a fuel injection valve actuator coupled to the I/O unit; and

a diagnosis indicator coupled to the I/O unit.

23. An apparatus to detect errors in a device, comprising:

a processor;

a memory module coupled to the processor;

an Error Detection Device (EDD) coupled to the memory module and the processor, wherein said memory module sends similar information to said EDD and said processor at the same time;

an Input/Output (I/O) unit coupled to the processor, wherein the I/O unit couples to the EDD;

a peripheral module coupled to the I/O unit; and

wherein said EDD detects errors in the information from the memory module as the device functions.