Method of forming a crystalline phase material

• US 20060243194A1
• Filed: 06/19/2006
• Published: 11/02/2006
• Est. Priority Date: 11/14/1996
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej S., Sharan, Sujit
• Granted Patent: US 7,625,641 B2
• Time in Patent Office: Days
• US Class Current: 117/84
• CPC Class Codes: C30B 1/02 by thermal treatment, e.g. strain annealing C30B1/12 takes precedence
• CPC Class Codes: C30B 29/34 Silicates
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/32053 of metal-silicide layers
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054

Abstract

A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO₂ and Si₃N₄, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Where the compressive stress inducing material is provided on the opposite side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is greater than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSi_x.

Claims

1. A semiconductor construction comprising:

a crystalline material layer over a substrate; and

compressive stress inducing atoms within the crystalline material layer, the compressive stress inducing atoms being present within the crystalline material layer at a concentration of from about 10¹⁶ atoms/cm³ to about 10²² atoms/cm³.

2. The semiconductor construction of claim 1 wherein the compressive stress inducing atoms comprise one or more of germanium atoms, tungsten atoms and cobalt atoms.

3. The semiconductor construction of claim 1 wherein the crystalline material is substantially of a C54 crystalline phase.

4. The semiconductor construction of claim 1 wherein the crystalline material is substantially of a C49 crystalline phase.

5. The semiconductor construction of claim 1 wherein the crystalline material layer is comprises by a patterned conductive line.

6. The semiconductor construction of claim 1 wherein the crystalline material comprises titanium silicide.

7. The semiconductor construction of claim 1 wherein the crystalline material comprises titanium silicide and the compressive stress inducing atoms comprise germanium atoms.

8. The semiconductor construction of claim 1 further comprising a compressive stress inducing material operably adjacent the crystalline material layer.

9. The semiconductor construction of claim 8 wherein the stress inducing material is over and in contact with the crystalline material layer.

10. The semiconductor construction of claim 8 wherein the stress inducing material is under and in contact with the crystalline material layer.