Memory cell array and method of manufacturing the same

• US 20060244024A1
• Filed: 05/02/2005
• Published: 11/02/2006
• Est. Priority Date: 05/02/2005
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Manger, Dirk, Tegen, Stefan, Muemmler, Klaus, Slesazeck, Stefan, Sieck, Alexander
• Granted Patent: US 7,473,952 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A memory cell array includes a plurality of active areas in which a plurality of memory cells are formed. A memory cell includes a storage capacitor, a transistor at least partially formed in a semiconductor substrate with a substrate surface, the transistor including a first source/drain region. A second source/drain region being formed adjacent to the substrate surface, a channel region connecting the first and second source/drain regions. The first source/drain region is formed adjacent to the substrate surface. The channel region is disposed in the semiconductor substrate, and a gate electrode. Rows of the active areas are separated from each other by isolation grooves that extend along a first direction. A first and a second word lines are disposed on either lateral sides of each of the rows of active areas. The first and the second word lines are connected with each other via the gate electrodes of the transistors of the corresponding row of active areas.

Claims

1. A memory cell array having a plurality of memory cells, the memory cell array comprising:

a plurality of active areas formed in a semiconductor substrate with a substrate surface, each active area having two lateral sides extending along a first direction, rows of active areas being separated from each other by isolation grooves extending along the first direction,

each memory cell including

a storage capacitor,

a transistor at least partially formed in one of the active areas, the transistor including

a first source/drain region which is connected with an electrode of the storage capacitor, the first source/drain region being formed adjacent to the substrate surface,

a second source/drain region being formed adjacent to the substrate surface,

a channel region connecting the first and second source/drain regions, the channel region being disposed in the active area, the channel region extending along the first direction; and

a gate electrode disposed along the channel region and being electrically isolated from the channel region by a gate isolating layer, the gate electrode controlling an electrical current flowing between the first and second source/drain regions,

wherein a first and a second word lines are disposed on either lateral sides of each of the rows of active areas, the first and the second word lines being connected with each other via the gate electrodes of the transistors of the corresponding row of active areas.

2. The memory cell array according to claim 1, wherein each of the gate electrodes has a top side, the top side of the gate electrode being disposed beneath the surface of the semiconductor substrate.

3. The memory cell array according to claim 1, wherein the channel region includes a fin-region in which the channel has the shape of a ridge, the ridge includes a top side and two lateral sides in a cross section perpendicular to a line connecting the first and second source/drain regions, and wherein the gate electrode is disposed at three sides of the ridge.

4. The memory cell array according to claim 2, wherein the channel region includes a fin-region in which the channel has the shape of a ridge, the ridge includes a top side and two lateral sides in a cross section perpendicular to a line connecting the first and second source/drain regions, and wherein the gate electrode is disposed at three sides of the ridge.

5. The memory cell array according to claim 1, wherein two word lines are disposed in each of the isolation grooves, the two word lines being isolated from each other and being assigned to two different rows of active areas.

6. The memory cell array according to claim 1, wherein the storage capacitor is a stacked capacitor.

7. The memory cell array according to claim 1, wherein the memory cells are arranged in rows and columns, respectively, the memory cells being arranged in the form of a regular grid.

8. The memory cell array according to claim 1, wherein the gate electrode has a bottom side, each of the first and second source/drain regions extending to a depth below or equal to the bottom side of the gate electrode.

9. The memory cell array according to claim 3, wherein each of the first and second source/drain regions extend to a depth below or equal to the top side of the ridge.

10. The memory cell array according to claim 4, wherein each of the first and second source/drain regions extend to a depth below or equal to the top side of the ridge.

11. The memory cell array according to claim 1, further comprising:

bit lines extending along a second direction intersecting the first direction, each of the second source/drain regions being connected with one bit line, wherein the bit lines are formed on the substrate surface to be in contact with a plurality of second source/drain regions.

12. The memory cell array according to claim 1, wherein an isolating spacer is disposed between the first source/drain region and the gate electrode and between the second source/drain region and the gate electrode, the isolating spacer having a larger thickness than the gate isolating layer.

13. The memory cell array according to claim 12, wherein the isolating spacer is made of silicon dioxide.

14. The memory cell according to claim 1, wherein each of the active areas of one row of active areas are isolated from each other by isolation trenches filled with an isolating material.

15. A method of manufacturing a memory cell array, comprising:

providing a semiconductor substrate having a substrate surface;

forming first and second openings in the substrate surface, the first openings having a larger depth than the second openings, the depth being measured from the substrate surface, two first openings being followed by one second opening, and one second opening being followed by two first openings;

defining isolation trenches in the semiconductor substrate, active areas being formed between two adjacent isolation trenches;

filling the isolation trenches with an isolating material;

providing a gate isolating layer on a bottom side of the second openings;

providing a conductive material in the second openings and on the side walls of the isolation trenches, gate electrodes being formed of the conductive material in the second openings and word lines being formed of the conductive material on the side walls of the isolation trenches;

providing an isolating material on the top side of the gate electrodes and between the word lines of one isolation trench;

providing first and second source/drain regions in the substrate material between the first and second openings in an active area;

forming a plurality of bit lines, one bit line being connected with a plurality of second source/drain regions;

forming a plurality of capacitor contacts, each of the capacitor contact being connected with the first source/drain region of a memory cell; and

forming a plurality storage capacitors, each of the storage capacitors being in contact with one of the capacitor contacts.

16. The method according to claim 15, wherein the first and second openings are defined using a hardmask comprising first, second and third stripes of a first, a second, and a third material, respectively, the first, second and third stripes being arranged parallel to each other, and each of the first, second and third material being able to be etched selectively to each other.

17. The method according to claim 15, wherein the depth of the first openings is equal to the depth of the isolation trenches, the depth being measured from the substrate surface.

18. The method according to claim 15, wherein, before forming the plurality of bit lines, the first and second source/drain regions are not masked, whereas the remaining portions of the surface are covered by an isolating material.

19. The method according to claim 16, wherein forming the plurality of bit lines includes depositing at least one layer of a conductive material and patterning the at least one layer so that as a result the bit lines are in contact with the second source/drain regions.

20. The method according to claim 17, wherein the at least one layer is photolithographically patterned using a mask having a lines/spaces pattern.

21. The method according to claim 15, wherein providing a conductive material includes the steps of conformally depositing the conductive material and anisotropically etching the conductive material.

22. The method according to claim 15, further comprising:

providing a first and a second lightly doped portions, after filling the isolation trenches with an isolating material, providing the first and second lightly doped portions includes;

providing an isolating material in the second opening; and

conducting an angled ion implantation step at an angle a between the substrate surface and a direction of the ions.

23. The method according to claim 15, further comprising:

removing the upper part of the isolating material from the isolation trenches to expose the upper part of the active area before providing the gate isolating layer, the gate isolating layer being formed on the exposed portions of the active area.

24. The method according to claim 23, wherein providing first and second source/drain regions includes:

providing a first and a second lightly doped portions,

after providing an isolating material on the top side of the gate electrodes and between the word lines of one isolation trench,

providing the first and second lightly doped portions being performed by conducting an angled ion implantation step at an angle α

between the substrate surface and a direction of the ions.