MULTIPLE OXIDE THICKNESSES FOR MERGED MEMORY AND LOGIC APPLICATIONS
First Claim
1. An electronic system comprising:
- a processor; and
an integrated circuit coupled to the processor, the integrated circuit including;
a top device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the top device having a top gate separated from the top surface by a top gate oxide; and
a trench device formed on a trench wall of the silicon wafer, wherein the trench wall has a (100) crystal plane orientation, the trench device having a trench gate separated from the trench wall by a trench gate oxide, wherein a thickness of the top gate oxide is different from a thickness of the trench gate oxide.
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Accused Products
Abstract
Structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, structures are provided for multiple gate oxide thicknesses on a single chip. The chip can include circuitry including but not limited to the memory and logic technologies. These structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. One structure includes a top layer of SiO2 on a top surface of a silicon wafer and a trench layer of SiO2 on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. The thickness of the top layer is different from a thickness of the trench layer.
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Citations
22 Claims
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1. An electronic system comprising:
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a processor; and
an integrated circuit coupled to the processor, the integrated circuit including;
a top device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the top device having a top gate separated from the top surface by a top gate oxide; and
a trench device formed on a trench wall of the silicon wafer, wherein the trench wall has a (100) crystal plane orientation, the trench device having a trench gate separated from the trench wall by a trench gate oxide, wherein a thickness of the top gate oxide is different from a thickness of the trench gate oxide. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor device, comprising;
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a logic device formed on a top surface of a silicon wafer having a (111) crystal plane orientation and a top gate oxide; and
a memory device formed on a trench wall of the silicon wafer, the trench wall having a (110) crystal plane orientation and a trench gate oxide. - View Dependent Claims (7, 8)
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9. A semiconductor device, comprising;
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a logic device formed on a top surface of a silicon wafer having a (111) crystal plane orientation and a top gate oxide; and
a memory device formed on a trench wall of the silicon wafer, the trench wall having a (311) crystal plane orientation and a trench gate oxide. - View Dependent Claims (10)
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11. An electronic system, comprising;
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a processor; and
an integrated circuit coupled to the processor, the integrated circuit including;
a logic device formed on a top surface of a silicon wafer having a (111) crystal plane orientation and a top gate oxide; and
a memory device formed on a trench wall of the silicon wafer, the trench wall having a (511) crystal plane orientation and a trench gate oxide. - View Dependent Claims (12)
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13. An electronic system, comprising;
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a processor; and
an integrated circuit coupled to the processor, the integrated circuit including;
a logic device formed on a top surface of a silicon wafer having a (100) crystal plane orientation and a top gate oxide; and
a memory device formed on a trench wall of the silicon wafer, the trench wall having a (110) crystal plane orientation and a trench gate oxide. - View Dependent Claims (14)
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15. An electronic system, comprising;
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a processor; and
a decode circuit, comprising;
a logic device formed on a top surface of a silicon wafer having a (100) crystal plane orientation and a top gate oxide; and
a memory device formed on a trench wall of the silicon wafer, the trench wall having a (110) crystal plane orientation and a trench gate oxide. - View Dependent Claims (16)
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17. An electronic system, comprising;
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a processor; and
a decode circuit, comprising;
a logic device formed on a top surface of a silicon wafer having a (100) crystal plane orientation and a top gate oxide; and
a memory device formed on a trench wall of the silicon wafer, the trench wall having a (311) crystal plane orientation and a trench gate oxide. - View Dependent Claims (18, 19)
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20. An electronic system, comprising;
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a processor; and
a decode circuit, comprising;
a logic device formed on a top surface of a silicon wafer having a (100) crystal plane orientation and a top gate oxide; and
a memory device formed on a trench wall of the silicon wafer, the trench wall having a (511) crystal plane orientation and a trench gate oxide. - View Dependent Claims (21, 22)
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Specification