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MULTIPLE OXIDE THICKNESSES FOR MERGED MEMORY AND LOGIC APPLICATIONS

  • US 20060244057A1
  • Filed: 07/17/2006
  • Published: 11/02/2006
  • Est. Priority Date: 08/31/1999
  • Status: Abandoned Application
First Claim
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1. An electronic system comprising:

  • a processor; and

    an integrated circuit coupled to the processor, the integrated circuit including;

    a top device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the top device having a top gate separated from the top surface by a top gate oxide; and

    a trench device formed on a trench wall of the silicon wafer, wherein the trench wall has a (100) crystal plane orientation, the trench device having a trench gate separated from the trench wall by a trench gate oxide, wherein a thickness of the top gate oxide is different from a thickness of the trench gate oxide.

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