Two terminal memory array having reference cells

• US 20060245241A1
• Filed: 06/29/2006
• Published: 11/02/2006
• Est. Priority Date: 07/20/2004
• Status: Active Grant

• Current Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Chevallier, Christophe, Rinerson, Darrell, Longcor, Steven
• Granted Patent: US 7,227,775 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Abstract

A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.

Claims

1. A memory comprising:

a memory array that includes a plurality of two-terminal memory cells;

a plurality of array lines that access the memory array;

at least one reference cell external to the memory array and accessed by at least some of the array lines, wherein the reference cell is a two-terminal memory cell and contributes to a reference level; and

a substrate positioned below the memory array and the reference cell, the substrate including,

address lines operable to carry address signals,

control lines operable to carry control signals,

data lines operable to carry data signals, and

a plurality of drivers that, as a function of the control signals, are operative to cause selected array lines to be placed at a first write voltage, a second write voltage, or a read voltage;

sensing circuitry, and

address decoding circuitry operative to decode the address signals on the address lines and to activate certain array lines;

wherein the two-terminal memory cells can be reversibly written to a first non-volatile resistive state when the selected array lines are at the first write voltage, reversibly written to a second non-volatile resistive state when the selected array lines are at the second write voltage, and produce a read output when the selected array lines are at the read voltage, and

wherein the sensing circuitry is operative to compare the read output to the reference level and produce data signals.

2. The memory of claim 1, wherein

the first write voltage places the two-terminal memory cells in a high resistive state,

the second write voltage places the two-terminal memory cells in a low resistive state, and

an effective resistance of the reference level is in-between the high resistive state and the low resistive state.

3. The memory of claim 2, wherein the reference level is derived from a combination of a plurality of reference cells, some of which are in the low resistive state and some of which are in the high resistive state.

4. The memory of claim 3, wherein the resistive states of each of the plurality of reference cells are intermediate to the high resistive state and the low resistive state.

5. The memory of claim 1, wherein the memory array is a cross point memory array.

6. A memory comprising:

a substrate including address lines and active circuitry, the active circuitry including sensing circuitry and address decoding circuitry, the address decoding circuitry in communication with the address lines;

addressable two-terminal memory plugs that are activated by the address decoding circuitry, each two-terminal memory plug operable to be reversibly written to a first resistive state at a first write voltage, reversibly written to a second resistive state at a second write voltage, and have its resistive state determined at a read voltage; and

at least one reference cell that contributes to a reference level, wherein the sensing circuitry is operative to produce an output that is a function of the resistive state of the activated two-terminal memory plug and the reference level, wherein the at least one reference cell is similar in structure to the two-terminal memory plugs,

wherein the addressable two-terminal memory plugs and the at least one reference cell are positioned over the substrate.

7. The memory of claim 6, wherein the reference level has an effective resistance that is intermediate to the first resistive state and the second resistive state.

8. The memory of claim 6, wherein the at least one reference cell includes a first terminal, a second terminal, and a programmable resistance, and

wherein the active circuitry is operative to apply a programming voltage across the first and second terminals to program the programmable resistance to a desired value.

9. The memory of claim 8, wherein the desired value is a selected one of a high resistive state, a low resistive state, or an intermediate resistive state.

10. The memory of claim 6, wherein the two terminal memory plugs are organized in an array and the least one reference cell is positioned outside of the array.

11. The memory of claim 10, wherein the array is a cross point memory array.

12. A memory comprising:

a substrate including address lines and active circuitry, the active circuitry including sensing circuitry and address decoding circuitry, the address decoding circuitry in communication with the address lines;

addressable two-terminal memory plugs that are activated by the address decoding circuitry, each two-terminal memory plug operable to be reversibly written to a first resistive state at a first write voltage, reversibly written to a second resistive state at a second write voltage, and have its resistive state determined at a read voltage; and

a reference level, wherein the sensing circuitry is operative to produce an output that is a function of the resistive state of the activated two-terminal memory plug and the reference level, and

wherein the addressable two-terminal memory plugs are positioned over the substrate.

13. A method of programming a reference cell, comprising:

providing a substrate that includes active circuitry, a two-terminal memory array positioned over the substrate, and at least one reference cell positioned outside of the two-terminal memory array and over the substrate; and

applying a programming voltage across a first terminal and a second terminal of the at least one reference cell, the applying operative to change a programmable resistance of the at least one reference cell to a desired value.

14. The method of claim 13, wherein the desired value is a selected one of a high resistive state, a low resistive state, or an intermediate resistive state.

15. The method of claim 13, wherein the active circuitry is coupled with the first and second terminals and is operative to apply the programming voltage across the first and second terminals.

16. A method of programming reference cells, comprising:

providing a substrate that includes active circuitry, a two-terminal memory array positioned over the substrate, and a plurality of reference cells positioned outside of the two-terminal memory array and positioned over the substrate;

applying a first programming voltage across a first terminal and a second terminal of a first one of the plurality of reference cells, the applying operative to change a programmable resistance of the first one of the plurality of reference cells to a first desired value; and

applying a second programming voltage across a first terminal and a second terminal of a second one of the plurality of reference cells, the applying operative to change a programmable resistance of the second one of the plurality of reference cells to a second desired value.

17. The method of claim 16, wherein the first desired value is indicative of a high resistive state.

18. The method of claim 16, wherein the second desired value is indicative of a low resistive state.

19. The method of claim 16 and further comprising:

applying a third programming voltage across a first terminal and a second terminal of a third one of the plurality of reference cells, the applying operative to change a programmable resistance of the third one of the plurality of reference cells to a third desired value.

20. The method of claim 19, wherein the third desired value is indicative of an intermediate resistive state.

21. The method of claim 16 and further comprising:

applying a programming voltage across a first terminal and a second terminal of at least one redundant reference cell that is included among the plurality of reference cells, the applying operative to change a programmable resistance of the at least one redundant reference cell to a desired value.

22. The method of claim 21, wherein the desired value is a selected one of a high resistive state, a low resistive state, or an intermediate resistive state.