Integrated power device having a start-up structure

• US 20060245258A1
• Filed: 03/31/2006
• Published: 11/02/2006
• Est. Priority Date: 04/04/2005
• Status: Active Grant

• Current Assignee: Stmicroelectronics France (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV), STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Saggio, Mario Giuseppe, Minnolo, Antonino Longo, Germana, Rosalia
• Granted Patent: US 7,700,970 B2
• Time in Patent Office: Days
• US Class Current: 365/185.220
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

An integrated power device includes a semiconductor body of a first conductivity type comprising a first region accommodating a start-up structure, and a second region accommodating a power structure. The two structures are separated from one another by an edge structure and are arranged in a mirror configuration with respect to a symmetry line of the edge structure. Both the start-up structure and the power structure are obtained using MOSFET devices. Both MOSFET devices are multi-drain MOSFET devices, having mesh regions, source regions and gate regions separated from one another. In addition, both MOSFET devices have drain regions delimited by columns that repeat periodically at a fixed distance. Between the two MOSFET devices there is an electrical insulation of at least 25 V.

Claims

1. An integrated power device comprising a semiconductor body of a first conductivity type housing a power structure, wherein said semiconductor body comprises a first region housing a start-up structure and a second region housing said power structure.

2. The device according to claim 1, wherein said power structure surrounds said start-up structure and said start-up structure and power structure are separated from one another by an edge structure.

3. The device according to claim 2, wherein said start-up structure and said power structure are arranged in a mirror configuration with respect to a symmetry line crossing said edge structure.

4. The device according to claim 1, wherein said start-up structure is a first MOSFET device and said power structure is a second MOSFET device.

5. The device according to claim 4, wherein said first and second MOSFET devices are multi-drain MOSFET devices, comprising respective body regions of a second conductivity type, respective gate regions arranged on top of said semiconductor body, respective source regions of said first conductivity type, and respective drain regions of said first conductivity type.

6. The device according to claim 5, further comprising column structures of said second conductivity type, which extend within said semiconductor body underneath and from said body regions and which separate from one another two distinct pluralities of drain regions.

7. The device according to claim 6, wherein said column structures repeat periodically and are equidistant from one another so as to maintain a fixed distance between said distinct drain regions of each plurality.

8. The device according to claim 5, comprising an edge structure extending between said first and second MOSFET devices and including two mesh regions that extend in a surface area of said semiconductor body and have said second conductivity type.

9. The device according to claim 8, wherein said mesh regions are distinct and are arranged specularly with respect to a symmetry line crossing said edge structure.

10. The device according to claim 8, wherein said edge structure further comprises column structures of said second conductivity type which extend within said semiconductor body underneath and from said mesh regions, said column structures having said second conductivity type and a higher doping level than said mesh regions.

11. The device according to claim 9, wherein said edge structure further comprises surface conductive regions extending on top of said semiconductor body.

12. The device according to claim 11, wherein said surface conductive regions comprise polysilicon regions distinct from one another, extending specularly with respect to said symmetry line, and a metal region extending on top of said polysilicon regions and electrically connected to one of said polysilicon regions.

13. The device according to claim 12, wherein said metal region forms a gate metallization for said first MOSFET device.

14. The device according to claim 8, wherein said edge structure provides an insulation of not less than 25 Volt.