SEMICONDUCTOR POWER DEVICE WITH PASSIVATION LAYERS

• US 20060246642A1
• Filed: 04/27/2006
• Published: 11/02/2006
• Est. Priority Date: 04/28/2005
• Status: Active Grant

• Current Assignee: Littelfuse Incorporated
• Original Assignee: IXYS Corporation (Littelfuse Incorporated)
• Inventors: Veeramma, Subhas Chandra Bose Jayappa
• Granted Patent: US 8,153,481 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/66128 Planar diodes
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor power device comprises a semiconductor substrate. The substrate includes an N-type silicon region and N+ silicon region. An oxide layer overlies the N− type silicon region, the oxide layer formed using a Plasma Enhanced Chemical Vapor deposition (PECVD) method. First and second electrodes are coupled to the N− type silicon region and the N+ type silicon region, respectively. The oxide layer has a thickness 0.5 to 3 microns. The power device also includes a polymide layer having a thickness of 3 to 20 microns; a first field plate overlying the oxide layer; and second field plate overlying the polymide layer and the first field plate, wherein the second field plate overlaps the first field plate by 2 to 15 microns.

Claims

1. A method of forming a power semiconductor device, the method comprising:

forming a first oxide layer directly on a semiconductor region of a first conductivity type using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method;

forming a second oxide layer directly on the first oxide layer using a PECVD method to form a first passivation layer comprising the first and second oxide layers; and

forming a second passivation layer on the first passivation layer.

2. The method of claim 1, wherein the first passivation layer has a thickness 3 microns or less, wherein the second passivation layer comprises polymide and has a thickness of at least 16 microns.

3. The method of claim 1, wherein the first passivation layer has a thickness 3 microns or less.

4. The method of claim 1, wherein the first passivation layer has a thickness about 0.5 micron to about 3 microns.

5. The method of claim 1, wherein the power device is a diode.

6. The method of claim 1, wherein the power device is a MOSFET or IGBT.

7. The method of claim 1, further comprising:

forming first and second field plates over the first passivation layer; and

forming a third passivation layer on the second passivation layer.

8. The method of claim 7, wherein the first field plate has a first portion that extends along a first lateral direction between the first and second passivation layers, and the second field plate has a second portion that extends along a second lateral direction between the second and third passivation layers, wherein the first and second portions define a curved path to the semiconductor region from the third passivation layer.

9. The method of claim 1, wherein the power device is a discrete device.

10. The method of claim 10, wherein the discrete power device is a diode, a MOSFET, or an IGBT.

11. A method of forming a power device, the method comprising:

forming a first passivation layer on an N−

silicon region;

forming a first field plate on the first passivation layer, the first field plate having a first portion that extends along a first lateral direction;

forming a second passivation layer on the first passivation layer;

forming a second field plate on the second passivation layer, the second field plate having a second portion that extends along a second lateral direction, the first and second portion overlapping each other to define a curved path to the substrate,

wherein the power device is provided with at least first and second metal electrodes to conduct electricity.

12. The method of claim 11, wherein the first passivation is formed directly on the N−

region using a Plasma Enhanced Chemical Vapor deposition (PECVD) method.

13. A semiconductor power device, comprising:

an oxide layer provided directly on an N−

type silicon region of a substrate, the oxide layer formed using a Plasma Enhanced Chemical Vapor deposition (PECVD) method; and

first and second electrodes coupled to first and second portions of the substrate.

14. The power device of claim 13, wherein the oxide layer has a thickness 0.5 to 3 microns.

15. The power device of claim 13, further comprising:

a polymide layer provided on the oxide layer, the polymide layer having a thickness of about 3 microns to about 20 microns.

16. The power device of claim 15, further comprising:

a first field plate overlying the oxide layer; and

a second field plate overlying the polymide layer and the first field plate,

wherein the second field plate overlaps the first field plate by 2 to 15 microns.