Recessed clamping diode fabrication in trench devices

• US 20060246650A1
• Filed: 06/13/2006
• Published: 11/02/2006
• Est. Priority Date: 05/25/1999
• Status: Active Grant

• Current Assignee: Michael E. Cornell, Richard K. Williams, Wai Tien Chan
• Original Assignee: Michael E. Cornell, Richard K. Williams, Wai Tien Chan
• Inventors: Williams, Richard K., Chan, Wai Tien, Cornell, Michael E.
• Granted Patent: US 7,592,228 B2
• Time in Patent Office: Days
• US Class Current: 438/212
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In a trench-gated MOSFET including an epitaxial layer over a substrate of like conductivity and trenches containing thick bottom oxide, sidewall gate oxide, and conductive gates, body regions of the complementary conductivity are shallower than the gates, and clamp regions are deeper and more heavily doped than the body regions but shallower than the trenches. Zener junctions clamp a drain-source voltage lower than the FPI breakdown of body junctions near the trenches, but the zener junctions, being shallower than the trenches, avoid undue degradation of the maximum drain-source voltage. The epitaxial layer may have a dopant concentration that increases step-wise or continuously with depth. Chained implants of the body and clamp regions permits accurate control of dopant concentrations and of junction depth and position. Alternative fabrication processes permit implantation of the body and clamp regions before gate bus formation or through the gate bus after gate bus formation.

Claims

1. A fabrication process for a semiconductor device, the process comprising:

(a.) forming a plurality of trenches in a substrate of a first conductivity type;

(b.) depositing a thick oxide on bottoms of the trenches;

(c.) forming a gate oxide layer on sidewalls of the trenches;

(d.) filling the trenches with a conductive material;

(e.) forming body regions of a second conductivity in the substrate in areas corresponding to one or more mesas that are between the trenches, wherein the body regions have a first depth;

(f.) forming clamp regions of the second conductivity in areas corresponding to one or more mesas that are between the trenches, wherein the clamp regions have a second depth that is greater than the first depth but shallower than the trenches;

(g.) forming active regions of the first conductivity type above the body regions; and

(h.) providing electrical connections to the conductive material, the active regions, and the substrate.

2. The process of claim 1, wherein step (a.) is performed before steps (e.) and (f.).

3. The process of claim 1, wherein steps (e.) and (f.) is performed before step (a.).

4. The process of claim 1, further comprising patterning the conductive material to form a gate bus overlying the substrate.

5. The process of claim 4, wherein forming the body regions comprises implanting dopants of the second impurity type through the gate bus.

6. The process of claim 4, wherein forming the clamp regions comprises implanting dopants of the second impurity type through the gate bus.

7. The process of claim 1, further comprising:

removing the conductive material from a surface of the substrate; and

forming a gate bus that contacts the conductive material and overlies portions of the substrate, wherein

forming the body regions and the clamp regions occurs after removing the conductive material from a surface of the substrate and before forming the gate bus.

8. The process of claim 1, wherein each of the trenches crosses one or more of the other trenches.