Cardiac pacemaker with table-based pacing mode implementation

• US 20060247708A1
• Filed: 04/28/2005
• Published: 11/02/2006
• Est. Priority Date: 04/28/2005
• Status: Active Grant

• Current Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Original Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Inventors: Esler, James A., Yost, David W., Birkholz, Doug M.
• Granted Patent: US 7,769,447 B2
• Time in Patent Office: Days
• US Class Current: 607/28
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/362 Heart stimulators heart defibrillators A61N1/39
• CPC Class Codes: A61N 1/3682 with a variable atrioventricular delay
• CPC Class Codes: A61N 1/39622 Pacing therapy

Abstract

A device and method for implementing a bradycardia pacing mode are disclosed which is mostly hardware-based but still allows the flexibility for making major changes in brady behavior normally found only in firmware-based implementations. The brady behavior of the device is encapsulated by a table in an area of RAM referred to as brady RAM, and the brady behavior can be changed by re-loading the brady RAM with a different table.

Claims

1. A cardiac pacemaker, comprising:

one or more timers, each timer having an output indicating the timer state and an input for changing the timer state;

sensing circuitry for generating a sensed event when an electrogram signal exceeds a specified threshold;

pacing circuitry for delivering a pacing pulse to a pacing electrode;

a brady RAM containing a brady table which maps particular device states defined by timer states and/or sensed events to associated device actions which include pacing pulse delivery and/or changes in timer states; and

,

brady hardware for comparing current timer states and sensed events to a device state contained in the brady table and, if found to match, causing performance of the associated device action.

2. The pacemaker of claim 1 further comprising:

a microprocessor which can access the brady RAM; and

,

a brady RAM controller enabled by the microprocessor for accessing the brady table stored in the brady RAM for use by the brady hardware.

3. The pacemaker of claim 1 wherein the brady table is made up of condition words representing particular device states and corresponding action words representing particular device actions.

4. The pacemaker of claim 3 wherein each condition word represents a particular device state according to whether particular bits of the word are set or cleared, and each action word represents particular actions which can be performed by the device according to whether particular bits of the word are set or cleared.

5. The pacemaker of claim 4 wherein the current state of the pacemaker is represented by a set of timer outputs and a set of sensing comparator outputs which form a current status word, and further wherein the condition words in the brady table are constructed with a bit-by-bit correspondence to the current status word.

6. The pacemaker of claim 4 wherein the actions which may be taken by the pacemaker in implementing a bradycardia pacing mode are represented by a set of action inputs which may include timer inputs and a set of pacing pulse generator inputs which cause delivery of paces to particular pacing electrodes, and further wherein the action words in the brady table are constructed with a bit-by-bit correspondence to the set of available action inputs.

7. The pacemaker of claim 6 wherein an action input is provided for causing a particular event represented in the current status word to be stored in a FIFO queue along with a time stamp.

8. The pacemaker of claim 4 further comprising a state change detector and wherein condition words are sequentially compared with the current status word when a bit of the current status word changes as detected by the state change detector.

9. The pacemaker of claim 5 wherein the current status word further comprises one or more state register outputs which are used to affect device behavior.

10. The pacemaker of claim 9 wherein a state register output signifies detection of a noisy condition in a particular sensing channel.

11. A method for implementing a bradycardia pacing mode in a cardiac pacemaker, comprising:

mapping particular device states defined by timer states and/or sensed events to associated device actions which include pacing pulse delivery and/or changes in timer states in a brady table contained in a brady RAM; and

,

comparing current timer states and sensed events to a device state contained in the brady table and, if found to match, causing performance of the associated device action.

12. The method of claim 11 further comprising accessing the brady RAM by means of a microprocessor and reloading the brady RAM with a different brady table to modify the pacing mode.

13. The method of claim 11 wherein the brady table is made up of condition words representing particular device states and corresponding action words representing particular device actions.

14. The method of claim 13 wherein each condition word represents a particular device state according to whether particular bits of the word are set or cleared, and each action word represents particular actions which can be performed by the device according to whether particular bits of the word are set or cleared.

15. The method of claim 14 wherein the current state of the pacemaker is represented by a set of timer outputs and a set of sensing comparator outputs which form a current status word, and further wherein the condition words in the brady table are constructed with a bit-by-bit correspondence to the current status word.

16. The method of claim 14 wherein the actions which may be taken by the pacemaker in implementing a bradycardia pacing mode are represented by a set of action inputs which may include timer inputs and a set of pacing pulse generator inputs which cause delivery of paces to particular pacing electrodes, and further wherein the action words in the brady table are constructed with a bit-by-bit correspondence to the set of available action inputs.

17. The method of claim 16 wherein an action input is provided for causing a particular event represented in the current status word to be stored in a FIFO queue along with a time stamp.

18. The method of claim 14 further comprising sequentially comparing condition words with the current status word when a bit of the current status word changes as detected by a state change detector.

19. The method of claim 15 wherein the current status word further comprises one or more state register outputs which are used to affect device behavior.

20. The method of claim 19 wherein a state register output signifies detection of a noisy condition in a particular sensing channel.