System and method for emulating a logic circuit design using programmable logic devices
First Claim
Patent Images
1. A method for partitioning a logic circuit design, the method comprising the steps of:
- recoding the logic circuit design;
assigning a first weight to each of one or more components to give a list of first weights, wherein each of the components comprises a memory component and a logic component;
assigning a second weight to each of one or more ports, the ports interconnecting the components, wherein the second weight is equal to a number of wires, wherein the wires interconnect the components;
generating a tree structure using the list of first weights; and
partitioning the tree structure using a tree-partitioning algorithm into a plurality of independent logic circuit designs, such that an original connectivity of each of the components is maintained.
0 Assignments
0 Petitions
Accused Products
Abstract
The present system provides a number of hardware and software modules that emulate logic circuit designs for simulation purposes. The present system receives an initial logic circuit design and provides algorithms to recode, weight partition and interconnect an emulated logic circuit wherein the features of the original circuit design are preserved. The system further provides a monitoring of the internal signals within the emulated circuit.
33 Citations
51 Claims
-
1. A method for partitioning a logic circuit design, the method comprising the steps of:
-
recoding the logic circuit design;
assigning a first weight to each of one or more components to give a list of first weights, wherein each of the components comprises a memory component and a logic component;
assigning a second weight to each of one or more ports, the ports interconnecting the components, wherein the second weight is equal to a number of wires, wherein the wires interconnect the components;
generating a tree structure using the list of first weights; and
partitioning the tree structure using a tree-partitioning algorithm into a plurality of independent logic circuit designs, such that an original connectivity of each of the components is maintained. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A method for emulating a logic circuit design using a plurality of programmable logic devices, the method comprising the steps of:
-
partitioning the logic circuit design into a plurality of independent logic circuit designs;
performing a memory transformation on a plurality of components of the independent logic circuit designs wherein each of the plurality of components comprises of a memory component and a logic component;
whereby the plurality of components are one of the plurality of programmable logic devices;
performing a monitoring transformation on the independent logic circuit designs to monitor a plurality of internal signals sent and received by the logic components; and
interconnecting the independent logic circuit designs using a time phase schedule for communication maintaining an original functionality of the logic circuit design. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
-
-
32. A method of communicating between a plurality of independent logic circuit designs, the method comprising:
-
connecting at least two of the independent logic circuit design with a plurality of signal-communicating paths;
communicating a plurality of signals between the independent logic circuit designs in a plurality of time phase schedules; and
sending the plurality of signals through the signal-communicating path in the plurality of time phase schedules. - View Dependent Claims (33, 34, 35, 36)
-
-
37. A system for partitioning a logic circuit design, comprising:
-
a recoding module for recoding an input logic circuit design into a recoded design for implementing a tree generation algorithm, a recoding module wherein the recoding module assigns a first weight to each component and assigns a second weight to each port of the logic circuit design;
a tree generation module for generating a tree structure from the recoded design using a list of weights; and
a partitioning module for partitioning the tree structure preserving the logic circuit design. - View Dependent Claims (38, 39, 40, 41)
-
-
42. A system for emulating a logic circuit design using a plurality of programmable logic devices, the system comprising:
-
a partitioning module for partitioning the logic circuit design into a plurality of independent logic circuit designs;
a memory extractor and mapper module for performing memory transformations by extracting a plurality of components of the independent logic circuit design wherein each of the plurality of components comprises of a memory component and a logic component, and mapping the memory component onto an external system memory;
a monitoring module for observing the visibility of an internal signal buried in the logic circuit design, on the plurality of programmable logic device; and
a time division multiplexing module for scheduling the plurality of nets. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50)
-
-
51. An application for emulating an input logic circuit design to an output logic circuit design suitable for execution on hardware, the application comprising:
-
a computing system including a long term memory, a processor readable memory and a processor, in communication with one another, the long term memory including a recoding module, the recoding module in communication with a processor and the processor readable memory, and when the user runs the application;
(a) the recoding module replaces a plurality of bi-directional ports connecting a plurality of the components in the logic circuit design with a plurality of unidirectional ports;
(b) the partitioning module for partitioning the logic circuit design into a plurality of independent logic circuit designs;
(c) the memory extractor and mapper module for performing memory transformations by extracting a plurality of components of the independent logic circuit design wherein each of the plurality of components comprises of a memory component and a logic component, and mapping the memory component onto an external system memory;
(d) the monitoring module for observing the visibility of internal signal buried in the logic circuit design, on the plurality of programmable logic device; and
(e) the time division multiplexing module for scheduling the nets;
wherein the recoded design is stored in a media and the recoded design is further transformed and transferred to a processor readable memory of a system including the processor readable memory and the processor when the media is used with the system.
-
Specification