Flash memory having configurable sector size and flexible protection scheme
First Claim
1. A method of storing data in a flash memory device comprising a memory array, said memory array comprising a plurality of memory sectors, wherein at least one of the memory sectors comprises a plurality of subsectors, said method comprising:
- receiving an instruction to erase an address contained in one of the plurality of subsectors;
checking a subsector enable bit in a configuration register;
if the subsector enable bit is not enabled, applying a first protection scheme to determine write protection of the address; and
if the subsector enable bit is enabled, applying a second protection scheme to determine write protection of the address, wherein the second protection scheme permits the control logic to unprotect a single subsector without unprotecting a remainder of the memory array.
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Accused Products
Abstract
Methods and systems are provided for a flash memory device having a configurable sector size and a flexible protection scheme. A flash memory circuit includes: a memory array including a plurality of memory sectors, wherein at least one of the memory sectors includes a plurality of subsectors; a status register array including a plurality of protection bits defining a protection scheme for the memory array; a configuration register array defining a protection scheme for the plurality of subsectors, said configuration register including a subsector enable bit and a plurality of subsector protection bits; and control logic for controlling storage of data on the memory array.
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Citations
14 Claims
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1. A method of storing data in a flash memory device comprising a memory array, said memory array comprising a plurality of memory sectors, wherein at least one of the memory sectors comprises a plurality of subsectors, said method comprising:
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receiving an instruction to erase an address contained in one of the plurality of subsectors;
checking a subsector enable bit in a configuration register;
if the subsector enable bit is not enabled, applying a first protection scheme to determine write protection of the address; and
if the subsector enable bit is enabled, applying a second protection scheme to determine write protection of the address, wherein the second protection scheme permits the control logic to unprotect a single subsector without unprotecting a remainder of the memory array. - View Dependent Claims (2, 3, 4)
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5. A flash memory circuit, comprising:
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a memory array comprising a plurality of memory sectors, wherein at least one of the memory sectors comprises a plurality of subsectors;
a status register array comprising a plurality of protection bits defining a protection scheme for the memory array;
a configuration register array defining a protection scheme for the plurality of subsectors, said configuration register comprising a subsector enable bit and a plurality of subsector protection bits; and
control logic for controlling storage of data on the memory array. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A flash memory circuit, comprising:
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a memory array comprising a plurality of memory sectors, wherein at least one of the memory sectors comprises a plurality of subsectors;
a configuration register array comprising a subsector enable bit; and
control logic for controlling storage of data on the memory array, said control logic configured such that if the subsector enable bit is enabled, the control logic performs erase instructions on a subsector level, and if the subsector enable bit is disabled, the control logic performs erase instructions on a sector level. - View Dependent Claims (12, 13, 14)
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Specification