Flash memory having configurable sector size and flexible protection scheme

• US 20060248267A1
• Filed: 04/29/2005
• Published: 11/02/2006
• Est. Priority Date: 04/29/2005
• Status: Abandoned Application

• Current Assignee: Chingis Technology Corporation (MediaTek, Inc.)
• Original Assignee: Programmable Microelectronics Corporation (Hsin-sheng Investment)
• Inventors: Xie, Jianhui
• Application Number:
  US11/119,041
• Publication Number:
  US 20060248267A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory

Abstract

Methods and systems are provided for a flash memory device having a configurable sector size and a flexible protection scheme. A flash memory circuit includes: a memory array including a plurality of memory sectors, wherein at least one of the memory sectors includes a plurality of subsectors; a status register array including a plurality of protection bits defining a protection scheme for the memory array; a configuration register array defining a protection scheme for the plurality of subsectors, said configuration register including a subsector enable bit and a plurality of subsector protection bits; and control logic for controlling storage of data on the memory array.

Claims

1. A method of storing data in a flash memory device comprising a memory array, said memory array comprising a plurality of memory sectors, wherein at least one of the memory sectors comprises a plurality of subsectors, said method comprising:

receiving an instruction to erase an address contained in one of the plurality of subsectors;

checking a subsector enable bit in a configuration register;

if the subsector enable bit is not enabled, applying a first protection scheme to determine write protection of the address; and

if the subsector enable bit is enabled, applying a second protection scheme to determine write protection of the address, wherein the second protection scheme permits the control logic to unprotect a single subsector without unprotecting a remainder of the memory array.

2. The method of claim 1, wherein:

said second protection scheme comprises a plurality of subsector protection bit, each of the subsector protection bits indicating a write protect state of one of the plurality of subsectors.

3. The method of claim 1, further comprising:

storing executable code in the plurality of sectors; and

storing configuration setting data in the plurality of subsectors.

4. The method of claim 3, wherein:

said executable code comprises code for operating a display device; and

said configuration setting data comprises configuration settings for the display device.

5. A flash memory circuit, comprising:

a memory array comprising a plurality of memory sectors, wherein at least one of the memory sectors comprises a plurality of subsectors;

a status register array comprising a plurality of protection bits defining a protection scheme for the memory array;

a configuration register array defining a protection scheme for the plurality of subsectors, said configuration register comprising a subsector enable bit and a plurality of subsector protection bits; and

control logic for controlling storage of data on the memory array.

6. The flash memory circuit of claim 5, wherein:

said control logic is configured such that enabling of the subsector enable bit allows the control logic to unprotect one of the subsectors without unprotecting a remainder of the memory array.

7. The flash memory circuit of claim 5, wherein:

said control logic is configured to check the subsector enable bit in response to receipt of an erase or program command targeting an address corresponding to one of the subsectors.

8. The flash memory circuit of claim 5, wherein:

said control logic is configured to check the subsector enable bit in response to receipt of an erase or program command targeting an address corresponding to one of the subsectors, and if the subsector enable bit is enabled, the control logic checks the subsector protection bit corresponding to the targeted address, and if the subsector enable bit is not enabled, the control logic checks the protection bit in the status register corresponding to the targeted address.

9. The flash memory circuit of claim 5, wherein:

said plurality of memory sectors store executable code; and

said plurality of subsectors store configuration setting data.

10. The flash memory circuit of claim 9, wherein:

said executable code comprises code for operating a display device; and

said configuration setting data comprises configuration settings for the display device.

11. A flash memory circuit, comprising:

a memory array comprising a plurality of memory sectors, wherein at least one of the memory sectors comprises a plurality of subsectors;

a configuration register array comprising a subsector enable bit; and

control logic for controlling storage of data on the memory array, said control logic configured such that if the subsector enable bit is enabled, the control logic performs erase instructions on a subsector level, and if the subsector enable bit is disabled, the control logic performs erase instructions on a sector level.

12. The flash memory circuit of claim 11, wherein:

said configuration register array further comprises;

one or more protection bits defining a first protection scheme for the memory array; and

a plurality of subsector protection bits defining a second protection scheme for the plurality of subsectors; and

said control logic is configured to check the subsector enable bit in response to an erase instruction for one of the subsectors, such that if the subsector enable bit is disabled, the control logic will perform the erase instruction pursuant to the first protection scheme, and if the subsector enable bit is enabled, the control logic will perform the erase instruction pursuant to the second protection scheme.

13. The flash memory circuit of claim 11, wherein:

said plurality of memory sectors store executable code; and

said plurality of subsectors store configuration setting data.

14. The flash memory circuit of claim 13, wherein:

said executable code comprises code for operating a display device; and

said configuration setting data comprises configuration settings for the display device.