Data rewriting method for flash memory using partial erases

• US 20060248269A1
• Filed: 06/29/2006
• Published: 11/02/2006
• Est. Priority Date: 12/17/2002
• Status: Active Grant

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Inventors: Shona, Yoshihiro
• Granted Patent: US 7,526,601 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups

Abstract

A data storage apparatus includes a flash memory and a control unit that controls the rewriting of data in the flash memory. The flash memory is divided into sectors, each of which is completely erasable in a time T. During a rewriting operation, multiple sectors are erased simultaneously for a time U less than T, and new data are written in a sector that has undergone multiple erasures and is now fully erased. The new data typically replace data stored in a sector that proceeds to be erased during multiple rewriting operations. The duration of each rewriting operation is reduced because the erasing process lasts for time U instead of time T.

Claims

1. A data storage apparatus, comprising:

a flash memory divided into sectors, each sector being completely erasable in a time T; and

a control unit that stores new data in the flash memory by executing a rewriting operation including erasing at least N sectors simultaneously for a time U less than the time T, where N is an integer greater than one, and writing the new data in a sector that has been erased N times, each time for the time U, and is now fully erased.

2. The data storage apparatus of claim 1, wherein the new data replace data stored in one of the at least N sectors erased in the rewriting operation.

3. The data storage apparatus of claim 2, wherein the control unit erases said one of the at least N sectors during N consecutive rewriting operations.

4. The data storage apparatus of claim 1, wherein the sectors in the flash memory include 2N buffer sectors and a plurality of data sectors, the new data being written in one of the 2N buffer sectors, the 2N buffer sectors including respective areas for storing addresses of the data sectors, the rewriting operation also including transferring data from another one of the 2N buffer sectors to one of the data sectors.

5. The data storage apparatus of claim 4, further comprising:

an address latch for storing the addresses of the data sectors to be erased in the rewriting operation; and

a read access redirection circuit for directing read access to the data sectors or the buffer sectors according to the addresses stored in the address latch.

6. The data storage apparatus of claim 1, wherein the sectors have physical addresses and the new data have a logical address, further comprising an address management memory with a plurality of areas for storing the physical addresses of a plurality of the sectors, the physical address of the sector in which the new data are written being stored in an area corresponding to the logical address.

7. The data storage apparatus of claim 6, wherein the control unit uses at least two of the sectors in the flash memory as an erase buffer for storing the physical addresses of sectors being erased and the physical addresses of sectors that have been fully erased and are available for storing the new data.