Systems and methods for CPU repair

• US 20060248314A1
• Filed: 02/17/2006
• Published: 11/02/2006
• Est. Priority Date: 02/18/2005
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Kuntz, Guy, Sedmak, Michael, Pomaranski, Ken, Barlow, Jeff, Brauch, Jeff, Joyal, Lacey, Hack, Stephen, Calkin, Howard, Gratias, Raymond
• Granted Patent: US 7,917,804 B2
• Time in Patent Office: Days
• US Class Current: 712/35
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0775 Content or structure details of the error report, e.g. specific table structure, specific error fields
• CPC Class Codes: G06F 11/0787 Storage of error reports, e.g. persistent data storage, storage using memory protection
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack

Abstract

Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.

Claims

1. A method for repairing a processor comprising the steps of:

initializing and executing an operating system;

determining that an allocated cache element is faulty using OS cache management logic;

de-allocating said processor;

swapping in a spare cache element for said faulty allocated cache element using non-OS cache management logic; and

re-allocating said processor.

2. The method of claim 1, further comprising the step of:

monitoring for a cache error while said operating system is executing; and

gathering and recording cache error information.

3. The method of claim 1, further comprising the step of:

determining whether said spare cache element is available if said allocated cache element is determined to be faulty using non-OS cache management logic.

4. The method of claim 3, further comprising the step of:

swapping in a spare processor for said de-allocated processor if said spare cache element is not available.

5. The method of claim 1, further comprising the step of:

reporting actions taken and updating cache configuration on a memory device.

6. A CPU cache element management system comprising:

at least one CPU having at least one allocated cache element and at least one non-allocated cache element;

OS cache management logic operable to determine whether allocated cache elements are faulty and operable to de-allocate said at least one CPU if at least one of said allocated cache elements is faulty; and

non-OS operable to swap in said non-allocated cache elements for said faulty allocated cache elements.

7. The CPU cache element management system of claim 6, wherein said OS cache management logic is further operable to monitor cache errors and record cache error information in a memory.

8. The CPU cache element management system of claim 7, wherein said cache error information is stored in a non-volatile memory.

9. The CPU cache management system of claim 6, wherein said non-OS cache management logic is further operable to determine whether at least one non-allocated cache element is available if said allocated cache element is determined to be faulty.

10. The CPU cache management system of claim 9, wherein said non-OS cache management logic is further operable to swap in a spare CPU for said de-allocated CPU if said at least one non-allocated cache element is not available.

11. The CPU cache management system of claim 6, wherein said cache management logic is further operable to report cache management actions taken and update a cache configuration stored on a memory device.

12. A computer system comprising:

at least one CPU having at least one allocated cache element and at least one spare cache element; and

OS cache management logic operable to determine whether said at least one allocated cache element is faulty and operable to de-allocate said at least on CPU; and

non-OS operable to swap in said at least one spare cache element for said faulty allocated cache element.

13. The computer system of claim 12, wherein said OS cache management logic is further operable to monitor cache errors and record cache error information in a memory.

14. The computer system of claim 13, wherein said cache error information is stored in a non-volatile memory.

15. The computer system of claim 12, wherein said non-OS cache management logic is further operable to determine whether said at least one spare cache element is available if said allocated cache element is faulty.

16. The computer system of claim 15, wherein said non-OS cache management logic is further operable to swap in a spare CPU for said de-allocated CPU if said at least one spare cache element is not available.

17. The computer system of claim 12, wherein said non-OS cache management logic is further operable to report cache management actions taken and update a cache configuration on a memory device.

18. A method for repairing a computer system having an operating system comprising the steps of:

monitoring at least one cache element associated with at least one CPU for at least one cache error;

recording cache error information associated with said at least one cache error;

determining whether said at least one cache element is faulty based on said cache error information using OS cache management logic;

de-allocating said at least on CPU;

determining if at least one spare cache element is available if said at least one cache element is faulty using non-OS cache management logic; and

swapping in said at least one spare cache element if said at least one spare cache element is available and said at least one cache element is faulty using non-OS cache management logic.

19. The method of claim 18, wherein said at least one cache element is determined to be faulty if a total number of errors occurring from said at least one cache element exceeds a predetermined threshold.

20. The method of claim 19, wherein said predetermined threshold is based on a total number of errors occurring from said cache element over a predetermined time period.

21. The method of claim 18 further comprising the step of:

determining whether a spare CPU is available if said at least one spare cache element is not available using non-OS cache management; and

swapping in said spare CPU for said de-allocated CPU if said spare CPU is available using non-OS cache management logic.

22. The method of claim 18 further comprising the step of:

updating a cache configuration in a memory.

23. A processor comprising:

a plurality of first memory portions;

a plurality of second memory portions;

OS logic for determining whether a first memory portion is faulty; and

non-OS logic for replacing the faulty first memory portion with a second memory portion during operation of the processor.

24. The processor of claim 23 wherein the OS logic for determining whether a first memory portion is faulty comprises logic for monitoring errors associated the first memory portion.

25. The processor of claim 23 wherein the OS logic for determining whether a first memory portion is faulty comprises logic for comparing a number of errors associated with the first memory portion to a threshold value.

26. The processor of claim 23 wherein the non-OS logic for replacing the faulty first memory portion with a second memory portion comprises logic for determining if a second memory portion is available for use in the replacement.

27. The processor of claim 23 wherein the OS logic for determining whether a first memory portion is faulty comprises logic for de-allocating the processor.

28. A processor comprising:

a first cache means configured for high-speed information storage and retrieval from the processor;

a second cache means for high-speed information storage and retrieval;

means, within operating system logic, for determining whether any portion of the first cache means configured for high-speed information storage is faulty; and

means, exclusive of said operating system logic, for replacing the faulty portion of the first cache means with at least a portion of the second cache means for high-speed information storage and retrieval.

29. The processor of claim 28 wherein the means for determining comprises means for monitoring errors associated the first cache means.

30. The processor of claim 28 wherein the means for determining comprises means for comparing a number of errors associated with the first cache means to a threshold value.

31. The processor of claim 28 wherein the means for replacing comprises means for determining if any portion of the second cache means is available for use in the replacement.

32. The processor of claim 28 wherein the means for determining comprises means for de-allocating the processor.