Apparatus and method for test and debug of a processor/core having advanced power management

• US 20060248394A1
• Filed: 04/26/2006
• Published: 11/02/2006
• Est. Priority Date: 04/27/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: McGowan, Robert A.
• Granted Patent: US 7,558,984 B2
• Time in Patent Office: Days
• US Class Current: 714/30
• CPC Class Codes: G06F 11/2242 in multi-processor systems, e.g. one processor becoming the test master G06F11/2736 takes precedence

Abstract

An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and switch units are coupled to each of the plurality of processor/cores. When the processor/cores have advanced power management systems, a sleep inhibit signal can be applied to the processor/core state machine preventing the state machine from entering a lower power state. The parameters of the processor/core can be tested to determine when the test and debug procedures can be implemented. When the (power) parameters are to low to permit test and debug, the test and debug unit can provide a command forcing the state machine into a state for which test and debug procedures can be implemented.

Claims

1. In a test and debug system, an apparatus for preventing a power-down of a selected processor/core, the apparatus comprising:

a test and debug unit, the test and debug unit generating a sleep-inhibit signal;

a plurality of processor/cores, the processor/cores including a power unit responsive to the sleep-inhibit signal, the power unit responsive to the sleep-inhibit signal, the sleep-inhibit signal preventing the decrease in power to the associated processor core; and

an interface unit providing an interface between the test and debug unit and the processor/cores, the interface unit receiving a sleep-inhibit signal for a selected processor/core, the interface unit applying the sleep-inhibit signal to the selected processor/core.

2. The apparatus as recited in claim 1 wherein the power unit includes a state machine, the sleep-inhibit signal applied to the state machine, the sleep inhibit signal preventing the state machine from transitioning to a lower power state.

3. The apparatus as recited in claim 2 further comprising a logic unit responsive to command signals for generating the sleep-inhibit signal.

4. The apparatus as recited in claim 3 further comprising a TAP unit and a test and debug unit, the TAP unit transferring a test and debug unit command to the logic unit, the logic unit translating the test and debug command to the sleep-inhibit signal.

5. The apparatus as recited in claim 2 wherein the sleep-inhibit signal does prevent transitions to lower power already in progress.

6. The apparatus as recited in claim 4 further including a register unit coupled to the logic unit for storing parameters resulting from the state of the state machine.

7. The apparatus as recited in claim 6 further comprising a test and debug unit, wherein, after the sleep inhibit signal has been applied to the state machine, the parameters associated with the state machine stored in thee register unit are transferred to the test and debug unit.

8. The apparatus as recited in claim 7 wherein the state machine controls at least one parameter selected from the group consisting of power parameters and clock parameters

9. A method for facilitating the test and debug of a plurality of processor/cores, the method comprising:

applying the sleep inhibit signal to a power unit of a selected processor/core, the sleep-inhibit signal preventing the selected processor from reducing power.

10. The method as recited in claim 9 further comprising controlling the sleep-inhibit signal by test and debug procedures.

11. The method as recited in claim 9 further comprising:

after applying the sleep-inhibit signal, testing the selected processor/core to determine whether the parameters permit the selected processor core to be tested.

12. The method as recited in claim 11 further comprising:

when the processor/core parameters do not permit testing the processor/core, forcing the parameters of the selected processor/core to a level wherein the selected processor core can be tested.

13. The method as recited in claim 12 wherein the forcing includes applying control signals from the logic unit to the state machine.

14. The method as recited in claim 13 wherein the forcing includes controlling at least one parameter selected from the group consisting of power parameter and clock parameters.

15. An apparatus for test and debug of a processor/core having an advanced power management system, the apparatus comprising:

a test and debug unit for generating test and debug commands;

a logic unit;

an interface TAP unit, the interface TAP unit providing an interface between the test and debug unit and the logic unit, wherein the logic unit can translate test and debug commands into control signals, one of the control signals being a sleep-inhibit signal;

a state machine coupled to the processor/core, state machine controlling the power of the processor/core by states controlling at least one of the power and the clock parameters, wherein the application of the sleep-inhibit signal to the state machine prevents the state machine from transitioning to a lower power.

16. The apparatus as recited in claim 15 further comprising a register unit, the register unit storing parameters associated with the processor/core, after application of the sleep-inhibit signal, the parameters associated with the processor/core are transferred to the test and debug unit to determine whether the parameters permit the test and debug of the processor/core, the test and debug unit generating a force command when the parameters do not permit the test and debug procedures, the force command translated by the logic unit, the logic unit applying force control signals resulting in parameters in the processor/core that permit test and debug.