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Apparatus and method for test and debug of a processor/core having advanced power management

  • US 20060248394A1
  • Filed: 04/26/2006
  • Published: 11/02/2006
  • Est. Priority Date: 04/27/2005
  • Status: Active Grant
First Claim
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1. In a test and debug system, an apparatus for preventing a power-down of a selected processor/core, the apparatus comprising:

  • a test and debug unit, the test and debug unit generating a sleep-inhibit signal;

    a plurality of processor/cores, the processor/cores including a power unit responsive to the sleep-inhibit signal, the power unit responsive to the sleep-inhibit signal, the sleep-inhibit signal preventing the decrease in power to the associated processor core; and

    an interface unit providing an interface between the test and debug unit and the processor/cores, the interface unit receiving a sleep-inhibit signal for a selected processor/core, the interface unit applying the sleep-inhibit signal to the selected processor/core.

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