Apparatus and method for controlling power, clock, and reset during test and debug procedures for a plurality of processor/cores

• US 20060248395A1
• Filed: 04/26/2006
• Published: 11/02/2006
• Est. Priority Date: 04/27/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: McGowan, Robert A.
• Granted Patent: US 7,536,597 B2
• Time in Patent Office: Days
• US Class Current: 714/30
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 11/2242 in multi-processor systems, e.g. one processor becoming the test master G06F11/2736 takes precedence
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

An interface unit is provided for use with a JTAG test and debug procedure involving a plurality of processor cores. The interface unit is provided with a logic unit that can translate test and debug commands into control signals. The control signals are applied to a power state machine coupled to a processor/core. The state of the power state machine can thereby be controlled and therefore the parameters of the associated processor/core, i.e., the power and clock parameters of the processor/core. In addition, the logic unit can generate control signals for activating switches, switches that controllably selective apply the TRST signal and the TMS signal to the TAP unit of the processor/core. This capability permits the TAP units of each processor/core to be synchronized.

Claims

1. An apparatus for controlling parameters of processor/core, the apparatus comprising:

a state machine coupled to the processor/core, the state machine controlling selected parameters of the processor/core, the state machine identifying the selected parameters of the processor/core;

a logic unit coupled to the state machine, the logic unit providing control signals forcing the state machine into a predetermined state in response to test and debug procedures, the predetermined state having the selected parameters.

2. The apparatus as recited in claim 1 further comprising a register bank coupled to the logic unit, the register bank storing the selected parameters.

3. The apparatus as recited in claim 1 wherein the selected parameters include at least one parameter selected from the group consisting of power parameters and clock parameters.

4. The apparatus as recited in claim 1 wherein the procedures are JTAG procedures.

5. The apparatus as recited in claim 1 wherein the processor/core includes a TAP unit, the apparatus further comprising a switch unit coupled the state machine of the TAP unit, the switch unit having a rest signal applied to an input terminal, the switch unit applying the reset signal to the TAP unit state machine in response to control signals from the logic unit, the control signals generated in response to test and debug signals.

6. The apparatus as recited in claim 5 further comprising an interface TAP unit, the interface TAP unit receiving test and debug signals, the interface TAP unit applying command signals to the logic unit, the command signals resulting in the generation of control signals.

7. The apparatus as recited in claim 6 wherein, in response to command signals from the test and debug procedure applied to the interface TAP unit, a selected parameter stored in the register unit is transferred to a test and debug unit.

8. A method for controlling selected parameters of a processor/core, the method comprising:

in response to test and debug commands applied to a logic unit, generating a control signal forcing the state of state machine coupled to the processor/core, the resulting state of the state machine controlling at least one selected parameter of the processor/core.

9. The method as recited in claim 8 wherein the generating a control signals includes:

applying the test and debug commands to an interface TAP unit; and

transferring the test and debug commands to the logic unit.

10. The method as recited in claim 8 further comprising storing preselected parameters of the processor/core resulting from a state of the state machine in a register unit.

11. The method as recited in claim 10 further comprising;

in response to a command signal from a test unit applied to an interface TAP unit, applying the command signal to the logic unit; and

transferring a preselected parameter from the register unit to the test unit.

12. The method as recited in claim 11 wherein the command signal forcing the state of the state machine is determined by the preselected parameter from the register unit.

13. An apparatus for controlling the power and clock parameters of a processor/core, the apparatus comprising;

a logic unit responsive to a first test command, the logic unit generating a first control signal;

a processor/core; and

a state machine coupled to the processor/core, the state machine determining the power and clock parameters, wherein the first control signal forces the state machine into a preselected state.

14. The apparatus as recited in claim 13 further comprising a register unit coupled to the logic unit, the register unit storing at least one parameter of the state of the state machine.

15. The apparatus as recited in claim 14 wherein the test commands are generated by a test unit, wherein in response to a second test command at least one parameter is transferred from the register unit to the test unit, the first control signal being generated in response to the at least one parameter.

16. The apparatus as recited in claim 13 further comprising a switch unit coupled to the processor/core, the switch unit having a reset signal applied to an input terminal of the switch unit, the reset signal being applied to the processor/core in response to a second control signal from the logic unit.