Power MOSFET device structure for high frequency applications

• US 20060249785A1
• Filed: 05/09/2005
• Published: 11/09/2006
• Est. Priority Date: 05/09/2005
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Lui, Sik K., Bhalla, Anup, Ng, Daniel, Li, Tiesheng
• Granted Patent: US 7,659,570 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

Claims

1. A metal oxide semiconductor field effect transistor (MOSFET) cell supported on a semiconductor substrate comprising:

an insulated gate electrode disposed on top of and extending over an epitaxial region of said semiconductor substrate surrounded by a body region of said MOSFET cell; and

a source electrode interposed into said insulated gate electrode and disposed above said epitaxial region for substantially preventing a coupling of an electrical field between said gate electrode and said epitaxial region.

2. The MOSFET cell of claim 1 wherein:

said source electrode further extends over said insulated gate for contacting a source region encompassed in said body region.

3. The MOSFET cell of claim 1 wherein:

said semiconductor substrate further includes a drain region disposed below and having a different dopant concentration than said epitaxial region.

4. The MOSFET cell of claim 1 wherein:

said insulated gate electrode further comprising an insulation layer for insulating said gate electrode from said source electrode wherein said insulation layer having a thickness depending on a Vgsmax rating of said MOSFET cell.

5. The MOSFET cell of claim 1 wherein:

said insulated gate electrode further comprising an insulation layer for insulating said gate electrode from said source electrode wherein said insulation layer having greater thickness surrounding an outer edges of said gate electrode for allowing an alignment tolerance for etching a contact opening.

6. The MOSFET cell of claim 5 wherein:

said MOSFET cell further comprising an insulation layer disposed between a pair of insulated gate insulating said source electrode from said epitaxial region wherein said insulation layer having a thickness substantially the same as said insulation layer surrounding an outer edges of said gate electrode.

7. The MOSFET cell of claim 1 wherein:

said MOSFET cell further comprising a N-channel MOSFET cell.

8. The MOSFET cell of claim 1 wherein:

said MOSFET cell further comprising a P-channel MOSFET cell.

9. A vertical power device supported on a semiconductor comprising a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite said first surface, wherein said vertical power device further comprising:

an insulated gate electrode disposed on top of said second surface for controlling a source to drain current; and

a source electrode interposed into said insulated gate electrode for substantially preventing a coupling of an electrical field between said gate electrode and an epitaxial region underneath said insulated gate electrode.

10. The vertical power device of claim 9 wherein:

said source electrode further covering and extending over said insulated gate for covering an area on said second surface of said semiconductor to contact said source region.

11. The vertical power device of claim 9 wherein:

said semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than said drain region.

12. The vertical power device of claim 9 wherein:

said insulated gate electrode further comprising an insulation layer for insulating said gate electrode from said source electrode wherein said insulation layer having a thickness depending on a Vgsmax rating of said vertical power device.

13. The vertical power device of claim 9 wherein:

said insulated gate electrode further comprising an insulation layer for insulating said gate electrode from said source electrode wherein said insulation layer having greater thickness surrounding an outer edges of said gate electrode for allowing an alignment tolerance for etching a contact opening.

14. The MOSFET cell of claim 13 wherein:

said MOSFET cell further comprising an insulation layer disposed between a pair of insulated gate insulating said source electrode from said epitaxial region, wherein said insulation layer having a thickness substantially the same as said insulation layer surrounding an outer edges of said gate electrode.

15. The vertical power device of claim 9 wherein:

said vertical power device further comprising a N-channel MOSFET cell.

16. The vertical power device of claim 9 wherein:

said vertical power device further comprising a P-channel MOSFET cell.

17. A switching device supported on a semiconductor comprising a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite said first surface, wherein said switching device further comprising:

an insulated gate electrode disposed on top of said second surface for controlling a source to drain current; and

a source electrode interposed into said insulated gate electrode for substantially preventing a coupling of an electrical field between said gate electrode and an epitaxial region underneath said insulated gate electrode.

18. The switching device of claim 17 wherein:

said source electrode further covering and extending over said insulated gate for covering an area on said second surface of said semiconductor to contact said source region.

19. The switching device of claim 17 wherein:

said semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than said drain region.

20. The switching device of claim 17 wherein:

said insulated gate electrode further comprising an insulation layer for insulating said gate electrode from said source electrode wherein said insulation layer having a thickness depending on a Vgsmax rating of said vertical power device.

21. The switching device of claim 17 wherein:

said insulated gate electrode further comprising an insulation layer for insulating said gate electrode from said source electrode wherein said insulation layer having greater thickness surrounding an outer edges of said gate electrode for allowing an alignment tolerance for etching a contact opening.

22. The switching device of claim 17 wherein:

said switching device further comprising a N-channel MOSFET cell.

23. The switching device of claim 17 wherein:

said switching device further comprising a P-channel MOSFET cell.

24. A method for manufacturing a power MOSFET device comprising a step of forming a body region and a source region in a semiconductor followed by depositing a gate layer on top of the semiconductor wherein said method further comprising:

applying contact mask for patterning a plurality of gates with an interposing opening patterned in said gates for allowing a layer of source metal to interpose into said gates.

25. The method of claim 24 further comprising:

depositing a metal layer over a plurality of patterned gates followed by a step applying a metal mask for patterning a gate metal and a source metal with said source layer interposing into said gates.