Highly configurable PLL architecture for programmable logic
2 Assignments
0 Petitions
Accused Products
Abstract
A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.
70 Citations
50 Claims
-
1-30. -30. (canceled)
-
31. A circuit for producing clock signals comprising:
-
a first multiplexer for selecting a reference signal from a plurality of input signals;
a PLL circuit for receiving the reference signal and producing a plurality of phase-shifted signals, wherein the phase-shifted signals have the same frequency and different phases;
a divider circuit for dividing the frequencies of at least two of the phase-shifted signals to produce a plurality of output clock signals; and
a second multiplexer for selecting one of the output clock signals. - View Dependent Claims (32, 33, 34, 35, 36)
-
-
37. A method for producing clock signals comprising:
-
selecting a reference signal from a plurality of input signals;
producing a plurality of phase-shifted signals, wherein the phase-shifted signals have the same frequency and different phases;
dividing the frequencies of at least two of the phase-shifted signals to produce a plurality of output clock signals; and
selecting one of the output clock signals. - View Dependent Claims (38, 39, 40, 41, 42)
-
-
43. A circuit for synchronously providing a reference signal to a PLL circuit that is enabled by a PLL enable signal comprising:
-
a multiplexer for selecting a reference signal from a plurality of clock signals;
a latch for receiving the PLL enable signal and outputting the current value of the PLL enable signal at an edge of the reference signal opposite to the edge of the reference signal to which the PLL circuit is aligned; and
an AND gate for providing the reference signal to the PLL circuit when the output of the latch is high;
whereby upon enabling the PLL circuit, the PLL circuit receives the reference signal before the PLL circuit latches on to the reference signal. - View Dependent Claims (44, 45, 46, 47, 48, 49, 50)
-
Specification