Integrated resonator structure and methods for its manufacture and use

• US 20060250198A1
• Filed: 05/09/2005
• Published: 11/09/2006
• Est. Priority Date: 05/09/2005
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Meltzer, David, Hargrove, Michael
• Granted Patent: US 7,268,645 B2
• Time in Patent Office: Days
• US Class Current: 333/185
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H03H 2001/0064 comprising semiconductor material

Abstract

An improved integrated LC resonator and methods for making and using the same are disclosed. The resonator includes (i) a first capacitor plate; (ii) an inductor over and in electrical communication with the first capacitor plate; and (iii) a second capacitor plate over and in electrical communication with the inductor. The method of making includes sequentially forming a first capacitor plate, a first dielectric layer thereon, a first via and an inductor, a second dielectric layer on the inductor, and a second via and a second capacitor plate. Each of the capacitor plates and the inductor are generally formed in different integrated circuit layers (for example, different metallization layers). Embodiments of the present invention can advantageously provide an integrated LC resonator tank having: (i) relatively high Q by reducing or minimizing parasitic effects; and (ii) relatively high shielding from the semiconductor substrate.

Claims

1. An integrated resonator, comprising:

a) a first capacitor plate in a first integrated circuit layer;

b) an inductor in a second integrated circuit layer, over and in electrical communication with said first capacitor plate; and

c) a second capacitor plate in a third integrated circuit layer, over and in electrical communication with said inductor.

2. The integrated resonator of claim 1, further comprising a first dielectric layer on said first capacitor plate, and a second dielectric layer on said inductor.

3. The integrated resonator of claim 2, wherein said inductor electrically communicates with (i) said first capacitor plate by a first via through said first dielectric layer and (ii) said second capacitor plate by a second via through said second dielectric layer.

4. The integrated resonator of claim 1, wherein said first integrated circuit layer comprises a first metal layer.

5. The integrated resonator of claim 1, further comprising a first dielectric layer on or in a semiconductor substrate, said first capacitor plate overlying said first dielectric layer.

6. The integrated resonator of claim 5, wherein said first capacitor plate is configured to shield said integrated resonator from a current in said semiconductor substrate.

7. The integrated resonator of claim 1, wherein said second and third integrated circuit layers each comprise a metal layer.

8. The integrated resonator of claim 7, wherein said first integrated circuit layer comprises a polysilicon layer.

9. The integrated resonator of claim 1, wherein said inductor consists essentially of a single metallization layer.

10. The integrated resonator of claim 1, wherein said first and second capacitor plates each include a plurality of slots.

11. The integrated resonator of claim 1, further comprising a semiconductor substrate and a shielding layer between said semiconductor substrate and said first capacitor plate.

12. The integrated resonator of claim 11, further comprising a first shield dielectric layer between said shielding layer and said semiconductor substrate, and a second shield dielectric layer between said shielding layer and said first capacitor plate.

13. The integrated resonator of claim 11, wherein said shielding layer comprises polysilicon.

14. The integrated resonator of claim 11, wherein said shielding layer is coupled to a predetermined voltage or a low impedance node.

15. The integrated resonator of claim 1, wherein said inductor comprises a center-tapped inductor.

21. A method of controlling a periodic signal frequency, comprising generating a periodic signal having a frequency, and coupling said periodic signal to the integrated resonator of claim 1.

23. The method of claim 21, wherein said shielding layer is configured to reduce, limit or minimize a current induced in said resonator by a corresponding current in said semiconductor substrate.

16. A method of making an integrated resonator, comprising the steps of:

a) forming a first capacitor plate;

b) forming a first dielectric layer on said first capacitor plate, said first dielectric layer having a first via hole therein;

c) forming a first via in said first via hole and an inductor on or in said first dielectric layer;

d) forming a second dielectric layer on said inductor, said second dielectric layer having a second via hole therein; and

e) forming a second via in said second via hole and a second capacitor plate on or in said second dielectric layer.

17. The method of claim 16, wherein the step of forming said first capacitor plate further includes forming a first plurality of slots in said first capacitor plate, and the step of forming said second capacitor plate further includes forming a second plurality of slots in said second capacitor plate.

18. The method of claim 16, wherein the step of forming said inductor includes forming said inductor in a substantially spiral shape.

19. The method of claim 16, further including, before the step of forming said first capacitor plate, the steps of:

a) forming a third dielectric layer over a semiconductor substrate; and

b) forming a shielding layer on or in said third dielectric layer.

20. The method of claim 16, wherein said shielding layer comprises polysilicon.

22. A method of shielding a resonator, comprising:

a) forming a shielding layer over a semiconductor substrate; and

b) forming said resonator above said shielding layer, said resonator comprising (i) a bottom capacitor plate in a first metal layer, (ii) an inductor in a second metal layer, over and in electrical communication with said bottom capacitor plate, and (iii) a top capacitor plate in a third metal layer, over and in electrical communication with said inductor.