Accurate persistent nodes
First Claim
Patent Images
1. A timing circuit, comprising:
- a power capture circuit for capturing power from a power source; and
a counter circuit coupled to the power capture circuit, the counter circuit providing a count that represents a progression of time.
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Abstract
A timing circuit that can function as an accurate persistent node in an RFID tag includes a power capture circuit for capturing power from a power source, and a counter circuit that provides a count representing a progression of time. The count can then be compared to a reference value representing a time constant of the circuit.
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Citations
63 Claims
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1. A timing circuit, comprising:
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a power capture circuit for capturing power from a power source; and
a counter circuit coupled to the power capture circuit, the counter circuit providing a count that represents a progression of time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 49)
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34. A timing circuit, comprising:
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a power capture circuit for capturing power from a power source, wherein the power capture circuit further comprises a subcircuit for comparing a voltage level of the power source to a voltage level of a node formed on the capacitance;
wherein if the voltage level of the power source is greater than a predetermined voltage level, the differential amplifier clamps the node to the power source, wherein if the voltage level of the power source drops below a level of the capacitance stored on the node, the node is isolated from the power source; and
a counter circuit coupled to the power capture circuit, the counter circuit providing a count that represents a progression of time, wherein the count is compared to a reference value representing a time constant of the circuit.
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35. A calibrated gate biasing circuit, comprising:
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a switched capacitor precision resistor; and
a voltage reference. - View Dependent Claims (36, 37, 38, 39, 40, 50)
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41. An electronic circuit for initiating a change in state of a host device, comprising:
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a counter coupled to a host device, the counter counting at a fixed interval, wherein the counter is reset to zero upon receiving a command from a remote device, wherein the count is compared to a reference value, wherein the host device changes states if the count matches the reference value, wherein operation of the counter continues in spite of an interruption in power supply from a power source. - View Dependent Claims (42, 51)
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43. A method for generating a timing signal, comprising:
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generating a count that represents a progression of time;
comparing the count to a reference value representing a time constant of the circuit; and
outputting a timing signal if the count matches the reference value. - View Dependent Claims (44, 45, 46)
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47. A method for counting Radio Frequency Identification (RFID) tags, comprising:
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interrogating each RFID tag in range of a reader;
receiving a tag identifier from each RFID tag;
instructing each tag to sleep upon receiving the tag identifier from the tag, wherein each tag remains in the sleep state for a known period of time, wherein the known period of time does not significantly vary regardless of whether the tag is powered or not, and generating a count of the tags. - View Dependent Claims (48)
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52. A method for counting Radio Frequency Identification (RFID) tags, comprising:
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interrogating each RFID tag in range of a reader;
receiving a tag identifier from each RFID tag;
instructing each tag to sleep upon receiving the tag identifier from the tag, wherein each tag automatically returns to a wake state after a time interval has elapsed, wherein the time interval is bounded between a minimum and a maximum value; and
generating a count of the tags. - View Dependent Claims (53, 54)
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55. An asymmetrical differential amplifier, comprising:
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a first transistor having a channel length of length A and a channel width of width B;
a second transistor having a different geometry than the first transistor such that the second transistor has a different threshold voltage than the first transistor, wherein the amount of bias is greater than the mismatch of the threshold voltages of the transistors of the differential amplifier. - View Dependent Claims (56, 57)
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58. An asymmetrical differential amplifier, wherein the differential amplifier has a first output when a source voltage is greater than a voltage on a node, wherein the differential amplifier has a second output when the source voltage is less than or equal to the voltage on the node.
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59. A circuit, comprising:
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an input node;
a storage node for storing an analog signal;
a coupling mechanism for selectively coupling the input and storage nodes to each other;
a control mechanism for controlling the coupling means responsive to the signal difference between the input node and the storage node. - View Dependent Claims (60, 61, 62, 63)
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Specification