Accurate persistent nodes

• US 20060250220A1
• Filed: 05/06/2005
• Published: 11/09/2006
• Est. Priority Date: 05/06/2005
• Status: Active Grant

• Current Assignee: Zest Labs, Inc.
• Original Assignee: Intelleflex Corporation
• Inventors: Stewart, Roger Green
• Granted Patent: US 7,728,713 B2
• Time in Patent Office: Days
• US Class Current: 340/10.400
• CPC Class Codes: G05F 3/16 being semiconductor devices
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06M 3/02 for performing an operation at a predetermined value of the count, e.g. arresting a machine G06M3/04 takes precedence
• CPC Class Codes: H03F 3/45076 characterised by the way of implementation of the active amplifying circuit in the differential amplifier

Abstract

A timing circuit that can function as an accurate persistent node in an RFID tag includes a power capture circuit for capturing power from a power source, and a counter circuit that provides a count representing a progression of time. The count can then be compared to a reference value representing a time constant of the circuit.

Claims

1. A timing circuit, comprising:

a power capture circuit for capturing power from a power source; and

a counter circuit coupled to the power capture circuit, the counter circuit providing a count that represents a progression of time.

2. The circuit of claim 1, wherein the power capture circuit includes a capacitor and a diode.

3. The circuit of claim 1, wherein the power capture circuit includes a differential amplifier and a capacitance.

4. The circuit of claim 3, wherein the differential amplifier compares a voltage level of the power source to a voltage level of a node formed on the capacitance;

wherein if the voltage level of the power source is greater than a specified voltage level, the differential amplifier clamps the node to the power source.

5. The circuit of claim 4, wherein the specified voltage level is based on a voltage level of the node.

6. The circuit of claim 4, wherein if the voltage level of the power source drops below a level of the capacitance stored on the node, the node is isolated from the power source.

7. The circuit of claim 4, wherein the power source generates a current from a wireless carrier signal.

8. The circuit of claim 4, wherein when the power source is equal to or less than a specified voltage level, the differential amplifier isolates the node from the power source.

9. The circuit of claim 3, further comprising a subcircuit for comparing a voltage level of the power source to a voltage level of a node formed on the capacitance;

wherein if the voltage level of the power source is greater than a predetermined voltage level, the differential amplifier clamps the node to the power source, wherein if the voltage level of the power source drops below a level of the capacitance stored on the node, the node is isolated from the power source.

10. The circuit of claim 9, wherein the power source generates a current from a wireless carrier signal.

11. The circuit of claim 3, wherein the differential amplifier is deliberately imbalanced.

12. The circuit of claim 1, wherein the counter circuit includes a reference oscillator for generating the count, wherein the reference oscillator is powered by power directed thereto from the power capture circuit.

13. The circuit of claim 12, wherein the reference oscillator functions for at least a predetermined amount of time after the power source ceases to provide power to the power capture circuit.

14. The circuit of claim 13, wherein the predetermined amount of time is greater than a maximum frequency hopping interval of a remote wireless device in wireless communication with the circuit.

15. The circuit of claim 14, wherein the predetermined amount of time is greater than a maximum frequency hopping interval for Radio Frequency Identification (RFID) devices as specified by the Federal Communications Commission (FCC) of the United States of America.

16. The circuit of claim 12, wherein the reference oscillator is a voltage controlled oscillator.

17. The circuit of claim 12, wherein the reference oscillator operates at substantially a constant frequency when operating.

18. The circuit of claim 12, further comprising a calibration matrix of digitally controlled diodes for calibrating a bias current of the oscillator.

19. The circuit of claim 18, wherein the calibration matrix is automatically calibrated upon detection of an event.

20. The circuit of claim 19, wherein the circuit self-calibrates from a single reference frequency.

21. The circuit of claim 20, wherein the reference frequency is derived from a signal from a remote device.

22. The circuit of claim 12, wherein the reference oscillator operates continuously.

23. The circuit of claim 12, wherein the reference oscillator operates on a current of less than about one microampere (μ

A).

24. The circuit of claim 12, wherein the reference oscillator operates on a current of less than about 1 nanoampere (nA).

25. The circuit of claim 12, wherein the reference oscillator operates on a current of less than about 10 picoamperes (pA).

26. The circuit of claim 12, further comprising a switched capacitor precision resistor for controlling a bias current to the reference oscillator.

27. The circuit of claim 12, further comprising an accumulating counter for generating the count based on input received or derived from an output of the reference oscillator, wherein the count is compared to a reference value representing a time constant of the circuit.

28. The circuit of claim 27, wherein the accumulating counter is reset by a command from a remote device.

29. The circuit of claim 1, wherein a reference value against which the count is compared is programmable by a remote device, the reference value representing a time constant of the circuit.

30. The circuit of claim 1, wherein the gate to source voltage across one or more transistors in the circuit is less than that transistor'"'"'s threshold voltage.

31. The circuit of claim 1, wherein the gate to source voltage across one or more transistors in the circuit is between about 100 mV below a threshold voltage of the transistor and about 100 mV above a voltage at a lowest leakage point of the transistor.

32. The circuit of claim 1, wherein the circuit operates at current levels at least about 10 times lower than a threshold voltage thereof, wherein the circuit operates at current levels at least about 10 times higher than at a lowest leakage point thereof.

33. The circuit of claim 1, wherein the circuit is embodied on a Radio Frequency Identification (RFID) tag.

49. An RFID system, comprising:

an RFID tag implementing the circuit of claim 1;

and

an RFID reader in communication with the RFID tag.

34. A timing circuit, comprising:

a power capture circuit for capturing power from a power source, wherein the power capture circuit further comprises a subcircuit for comparing a voltage level of the power source to a voltage level of a node formed on the capacitance;

wherein if the voltage level of the power source is greater than a predetermined voltage level, the differential amplifier clamps the node to the power source, wherein if the voltage level of the power source drops below a level of the capacitance stored on the node, the node is isolated from the power source; and

a counter circuit coupled to the power capture circuit, the counter circuit providing a count that represents a progression of time, wherein the count is compared to a reference value representing a time constant of the circuit.

35. A calibrated gate biasing circuit, comprising:

a switched capacitor precision resistor; and

a voltage reference.

36. The circuit of claim 35, wherein the voltage reference includes a matrix of forward biased diodes coupled to an outlet of the switched capacitor precision resistor.

37. The circuit of claim 36, wherein the matrix is calibrated based on a reference frequency.

38. The circuit of claim 37, wherein the reference frequency is received from a remote device.

39. The circuit of claim 35, wherein the current being controlled is less than about 10 picoamperes (pA).

40. The circuit of claim 35, wherein the circuit is embodied on a Radio Frequency Identification (RFID) tag.

50. An RFID system, comprising:

an RFID tag implementing the circuit of claim 35;

and

an RFID reader in communication with the RFID tag.

41. An electronic circuit for initiating a change in state of a host device, comprising:

a counter coupled to a host device, the counter counting at a fixed interval,

wherein the counter is reset to zero upon receiving a command from a remote device,

wherein the count is compared to a reference value,

wherein the host device changes states if the count matches the reference value,

wherein operation of the counter continues in spite of an interruption in power supply from a power source.

42. The circuit of claim 41, wherein the circuit is embodied on a Radio Frequency Identification (RFID) tag.

51. An RFID system, comprising:

an RFID tag implementing the circuit of claim 41;

and

an RFID reader in communication with the RFID tag.

43. A method for generating a timing signal, comprising:

generating a count that represents a progression of time;

comparing the count to a reference value representing a time constant of the circuit; and

outputting a timing signal if the count matches the reference value.

44. The method of claim 43, further comprising capturing power from a wireless signal, wherein the power powers a mechanism for generating the count.

45. The method of claim 44, wherein generating the count continues at least until the count matches the reference value even when no power is being captured from the wireless signal.

46. The method of claim 43, wherein the count is reset upon receiving a command from a remote device.

47. A method for counting Radio Frequency Identification (RFID) tags, comprising:

interrogating each RFID tag in range of a reader;

receiving a tag identifier from each RFID tag;

instructing each tag to sleep upon receiving the tag identifier from the tag,

wherein each tag remains in the sleep state for a known period of time,

wherein the known period of time does not significantly vary regardless of whether the tag is powered or not, and

generating a count of the tags.

48. The method of claim 47, wherein each tag is interrogated only once prior to generating the count.

52. A method for counting Radio Frequency Identification (RFID) tags, comprising:

interrogating each RFID tag in range of a reader;

receiving a tag identifier from each RFID tag;

instructing each tag to sleep upon receiving the tag identifier from the tag,

wherein each tag automatically returns to a wake state after a time interval has elapsed,

wherein the time interval is bounded between a minimum and a maximum value; and

generating a count of the tags.

53. The method of claim 52, wherein the time interval does not significantly vary regardless of whether the tag is powered or not.

54. The method of claim 52, wherein the maximum ratio of maximum value to minimum value is less than 10:

1.

55. An asymmetrical differential amplifier, comprising:

a first transistor having a channel length of length A and a channel width of width B;

a second transistor having a different geometry than the first transistor such that the second transistor has a different threshold voltage than the first transistor,

wherein the amount of bias is greater than the mismatch of the threshold voltages of the transistors of the differential amplifier.

56. The differential amplifier of claim 55, wherein the channel length of the second transistor is different than the channel length of the first transistor.

57. The differential amplifier of claim 55, wherein the channel width of the second transistor is different than the channel width of the first transistor.

58. An asymmetrical differential amplifier, wherein the differential amplifier has a first output when a source voltage is greater than a voltage on a node, wherein the differential amplifier has a second output when the source voltage is less than or equal to the voltage on the node.

59. A circuit, comprising:

an input node;

a storage node for storing an analog signal;

a coupling mechanism for selectively coupling the input and storage nodes to each other;

a control mechanism for controlling the coupling means responsive to the signal difference between the input node and the storage node.

60. The circuit of claim 59, wherein the control mechanism includes a differential amplifier with one input responsive to the input node and another input responsive to the storage node.

61. The circuit of claim 59, wherein the analog signal is a voltage level.

62. The circuit of claim 59, wherein the circuit is a sampling circuit.

63. The circuit of claim 59, wherein the circuit is a peak detector circuit.