Random access memory with stability enhancement and early ready elimination

• US 20060250860A1
• Filed: 07/06/2006
• Published: 11/09/2006
• Est. Priority Date: 11/10/2004
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Rajiv V. Joshi
• Inventors: Joshi, Rajiv V.
• Granted Patent: US 7,274,590 B2
• Time in Patent Office: Days
• US Class Current: 365/191
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A random access memory includes a memory cell having an access device. The access device is switched on or off in accordance with a signal on a wordline to conduct a memory operation through the access device. A logic circuit is coupled to the wordline to delay or gate the wordline signal until an enable signal has arrived at the logic circuit. The access device improves stability and eliminates early read problems.

Claims

1. A random access memory, comprising:

a memory cell including at least one access device, the at least one access device being switched on or off in accordance with a signal on a wordline to conduct a memory operation through the at least one access device; and

a logic circuit coupled to the wordline to gate the wordline signal until an enable signal has arrived at the logic circuit.

2. The memory as recited in claim 1, wherein the memory cell includes a static random access memory cell.

3. The memory as recited in claim 1, wherein the at least one access device includes a bitline transistor.

4. The memory as recited in claim 1, wherein the logic circuit includes a transistor which selectively couples the wordline to a gate of the at least one access device.

5. The memory as recited in claim 4, wherein the selective coupling of the transistor to the wordline is controlled by the enable signal which includes a bit decode signal.

6. The memory as recited in claim 1, wherein the enable signal is timed by a system clock signal.

7. The memory as recited in claim 1, further comprising a bit select circuit having cross-coupled transistors gated by a bit decode signal, wherein the cross-coupled transistors are sized to improve performance of memory operations.

8. A static random access memory, comprising:

a memory cell including first and second access transistors respectively coupled to first and second bitlines, the first and second access transistors having gates coupled to a connection node; and

a logic circuit coupled to a wordline, the logic circuit selectively coupling the wordline to the connection node in accordance with an enable signal, such that a trigger signal on the wordline is synchronized with bit line signals to reduce or eliminate an early read condition.

9. The memory as recited in claim 8, wherein the logic circuit includes a transistor, which selectively couples the wordline to the connection node.

10. The memory as recited in claim 9, wherein the selectively coupling of the connection node to the wordline is controlled by an enable signal, which includes a bit decode signal.

11. The memory as recited in claim 10, wherein the enable signal is timed by a system clock signal.

12. The memory as recited in claim 8, further comprising a bit select circuit having cross-coupled transistors gated by a bit decode signal, wherein the cross-coupled transistors are sized to improve performance of memory operations.