Semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories)
First Claim
1. A semiconductor memory component comprising:
- a memory cell array, including data word groups having a desired number of memory cells storing data bits;
a test write register for buffer-storing a primary test data word read into the memory cell array at a test address; and
comparator units for comparing mutually corresponding data bits of the respective primary test data word and of a secondary test data word read out from the memory cell array from the test address, in which case, when mutually corresponding data bits in the primary and secondary test data words match, an error free signal is generated in each case on PF signal lines respectively assigned to one of the comparator units,
4 Assignments
0 Petitions
Accused Products
Abstract
A semiconductor component and method of testing a semiconductor component is disclosed. The invention relates to the parallel testing of semiconductor memory components having a fully functional memory area, which are classified as all good memory, and of semiconductor memory components having a restricted memory area, which are classified as partial good memory. For testing semiconductor memory components classified as partial good memory, the result, independently of the result of the comparison for those test addresses which are assigned to a memory area outside the functional memory area of the semiconductor memory component classified as partial good memory, is overwritten with an error free signal and a semiconductor memory component classified as all good memory is simulated. The testing of semiconductor memory components classified as partial good memory is accelerated and simplified.
-
Citations
21 Claims
-
1. A semiconductor memory component comprising:
-
a memory cell array, including data word groups having a desired number of memory cells storing data bits;
a test write register for buffer-storing a primary test data word read into the memory cell array at a test address; and
comparator units for comparing mutually corresponding data bits of the respective primary test data word and of a secondary test data word read out from the memory cell array from the test address, in which case, when mutually corresponding data bits in the primary and secondary test data words match, an error free signal is generated in each case on PF signal lines respectively assigned to one of the comparator units, - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A semiconductor memory component comprising:
-
a memory cell array, including data word groups having a desired number of memory cells;
a plurality of data lines connected to a respective one of the memory cells of the data word groups suitable for transmitting data bits stored in the memory cells;
a plurality of internal address lines configured for a desired address space in the memory cell array to be addressed by means of the internal address lines;
a test write register for buffer-storing a primary test data word read into the memory cell array at a test address; and
comparator units for comparing mutually corresponding data bits of the respective primary test data word and of a secondary test data word read out from the memory cell array from the test address, in which case, when mutually corresponding data bits in the primary and secondary test data words match, an error free signal is generated in each case on PF signal lines respectively assigned to one of the comparator units, further comprising an error address memory for storing an error address identifying a nonfunctional partial area of the desired address space, and an address comparator for comparing the respective test address with the error address, in which case, when the test address matches the error address, an error free signal is constrained in each case on the PF signal lines. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
-
-
18. A method for testing semiconductor wafers having semiconductor memory components each having a memory cell array, which in each case has a desired address space predefined by a desired number of addressing lines and a desired I/O area predefined by a desired number of data lines the memory cell arrays being functional to different extents, comprising:
-
functionally testing the memory cell arrays of the semiconductor memory components in a prefuse memory test;
replacing nonfunctional areas of the memory cell arrays by activating redundant memory cells;
storing an error address identifying an irreparable memory area within the desired address space in an error address memory in semiconductor memory components having a restricted memory area; and
functionally testing the semiconductor memory components in a postfuse memory test by writing in and reading out test data words at test addresses within the desired address space, an error-free behavior of the respective irreparable memory area being simulated in semiconductor memory components having a memory area with restricted functionality when the respective test address matches the error address. - View Dependent Claims (19, 20)
-
-
21. A semiconductor memory component comprising:
-
a memory cell array, including data word groups having a desired number of memory cells configured to store data bits;
means for buffer-storing a primary test data word read into the memory cell array at a test address; and
comparator means for comparing mutually corresponding data bits of the respective primary test data word and of a secondary test data word read out from the memory cell array from the test address, in which case, when mutually corresponding data bits in the primary and secondary test data words match, an error free signal is generated in each case on PF signal lines respectively assigned to one of the comparator means, further comprising means for storing an error address identifying a nonfunctional partial area of the desired address space, and an address comparator for comparing the respective test address with the error address, in which case, when the test address matches the error address, an error free signal is constrained in each case on the signal lines.
-
Specification