AC sensing for a resistive memory

• US 20060250872A1
• Filed: 07/07/2006
• Published: 11/09/2006
• Est. Priority Date: 10/09/2003
• Status: Active Grant

• Current Assignee: Thomas W. Voshell
• Original Assignee: Thomas W. Voshell
• Inventors: Voshell, Thomas W.
• Granted Patent: US 7,263,017 B2
• Time in Patent Office: Days
• US Class Current: 365/207
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2013/0057 Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits

Abstract

Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory device can include the array and peripheral circuitry for reading or sensing each memory cell in the array. The peripheral circuitry can include a clock/control circuit providing a control signal, which controls when a row of memory cells are sensed, a switching circuit for receiving a cellplate count signal and a bit count signal provided by the clock/control circuit, a cellplate line signal and a bit line signal from the memory cell, the switching circuit producing a first output signal and a second output signal, wherein one of the first output signal and the second output signal is at a supply voltage and the other of the first output signal and the second output signal alternates polarity with each sensing operation and a comparison circuit receiving the first output signal and the second output signal and outputting a signal corresponding to the logic sate of the memory cell.

Claims

1-18. -18. (canceled)

19. An apparatus for sensing a logic state of a memory cell, comprising:

a control circuit providing a control signal to said memory cell, said control signal controlling when said memory cell is sensed;

a switching circuit that receives a cellplate count signal and a bit count signal provided by said control circuit, said switching circuit further receiving a cellplate line signal and a bit line signal from said memory cell, said switching circuit producing a first output signal and a second output signal; and

a comparison circuit receiving said first and second output signals and outputting a signal corresponding to the logic state of said memory cell.

25. A memory device comprising:

an array of memory cells;

a cellplate line common across said array of memory cells; and

an apparatus for sensing a logic state of one of said memory cells, said apparatus comprising;

first and second sensing lines between which are connected to a memory element having at least two resistive memory states,

switching circuitry that provides sensing current through the memory element, and

output circuitry that receives said sensing current and, in response, provides an output signal indicating a resistance state of said memory element.

26. A processing system, comprising:

a processor; and

a memory device for exchanging data with said processor, said memory device comprising;

an array of memory cells;

a cellplate line common across said array of memory cells, and

an apparatus for sensing a logic state of one of said memory cells, said apparatus comprising;

first and second sensing lines between which are connected a memory element having at least two resistive memory states;

switching circuitry that provides sensing current through the memory element; and

output circuitry that receives said sensing current and, in response, provides an output signal indicating a resistance state of said memory element.

27. An integrate circuit comprising:

a memory device comprising;

an array of memory cells,

a cellplate line common across said array of memory cells, and

an apparatus for sensing a logic state of one of said memory cells, said apparatus comprising;

first and second lines between which are connected a memory element having at least two resistive memory states;

switching circuitry that provides sensing current through the memory element; and

output circuitry that receives said sensing current and, in response, provides an output signal indicating a resistance state of said memory element.

28. A processing system, comprising:

a processor; and

a memory device for exchanging data with said processor, said memory device comprising;

an array of memory cells,

a cellplate line common across said array of memory cells, and

an apparatus for sensing a logic state of a memory cell, comprising;

an apparatus for sensing a logic state of memory cell, comprising;

a control circuit providing a control signal, said control signal controlling when said memory cell is sensed;

a switching circuit that receives a cellplate count signal and a bit count signal provided by said control circuit, said switching circuit further receiving a cellplate line signal and a bit line signal from said memory cell, said switching circuit producing a first output signal and a second output signal; and

a comparison circuit receiving said first and second output signals and outputting a signal corresponding to the logic state of said memory cell.