Circuit and method for operating a delay-lock loop in a power saving manner

• US 20060250877A1
• Filed: 07/07/2006
• Published: 11/09/2006
• Est. Priority Date: 03/11/2005
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Scott Smith, Tyler Gomm
• Inventors: Smith, Scott, Gomm, Tyler
• Granted Patent: US 7,218,568 B2
• Time in Patent Office: Days
• US Class Current: 365/229
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A control circuit for a delay-lock loop having a delay line and a phase detector is used in a memory device. In a standby mode, the control circuit isolates a reference clock signal from the delay-lock loop to save power unless a clock signal generated by the loop is needed for a memory operation. However, the reference signal is periodically coupled to the delay line for a sufficient period to achieve a locked condition. As a result, the phase of the output signal from delay-lock loop can be quickly locked to the phase of the reference signal when a memory operation is to occur during a normal operating mode. When transitioning between the standby mode and the normal operating mode, the control circuit couples the reference clock signal to the delay line for at least a predetermined period of time.

Claims

1. A method of operating a delay-lock loop included in a memory device, the method comprising:

in a normal operating mode of the memory device, continuously coupling a reference clock signal to a delay line used in the delay-lock loop; and

in a standby mode of the memory device;

entering a standby period in which the reference clock signal is isolated from the delay line; and

while in the standby period, periodically coupling the reference clock signal to the delay line for an update period of sufficient duration to allow the delay-lock loop to achieve a locked condition, and then re-entering the standby period.

2. The method of claim 1, further comprising, when the memory device enters the normal operating mode, coupling the reference clock signal to the delay line for at least a predetermined period.

3. The method of claim 1, further comprising:

detecting when a bank of memory cells in the memory device becomes active when the memory device is in the standby mode; and

coupling the reference clock signal to the delay line used in the delay-lock loop responsive to detecting that the bank of memory cells has become active.

4. The method of claim 1, further comprising:

determining if the delay-lock loop is in a locked condition when entering the standby mode;

if the determination is made that the delay-lock loop is in a locked condition when entering the standby mode, immediately isolating the reference clock signal from the delay line; and

if the determination is made that the delay-lock loop is not in a locked condition when entering the standby mode, continuing to couple the reference clock signal to the delay line for a predetermined period before isolating the reference clock signal from the delay line.

5. The method of claim 1, further comprising:

determining if the delay-lock loop is being reset when the memory device is in the standby mode; and

in response to determining that the delay-lock loop is being reset, coupling the reference clock signal to the delay line for a reset period before isolating the reference clock signal from the delay line.

6. The method of claim 5 wherein the reset period is substantially longer than the update period.

7. The method of claim 1, further comprising:

determining if memory device is transitioning from the standby mode to the normal operating mode; and

in response to determining that the memory device is transitioning from the standby mode to the normal operating mode, coupling the reference clock signal to the delay line for a period that is substantially longer than the update period.

8. The method of claim 1 wherein the memory device is operable in a refresh mode in which refresh signals are generated internally in the memory device, and wherein the method further comprises:

determining if memory device is transitioning from the refresh mode in which refresh signals are generated internally in the memory device, and

in response to determining that the memory device is transitioning out of the refresh mode in which refresh signals are generated internally in the memory device, coupling the reference clock signal to the delay line for a period that is substantially longer than the update period.

9. The method of claim 8 wherein the refresh mode in which refresh signals are generated internally in the memory device comprises a self-refresh mode.

10. The method of claim 1 wherein the delay-lock loop further comprise a phase detector having first and second input terminals receiving the reference clock signal and an output signal from the delay line, the phase detector being operable to generate an output signal that controls the delay of the delay line, the method further comprising selectively enabling and disabling the phase detector when the memory device is operating in the standby mode.

11. The method of claim 10 wherein the memory device is operable in an on die termination mode, and wherein the method further comprises disabling the phase detector in the on die termination mode while coupling the reference clock signal to the delay line when the memory device is operating in the standby mode.

12. The method of claim 1 wherein the memory device comprises a mode register that is programmable responsive to a load mode command, and wherein the method further comprises:

detecting the load mode command, and

when in the standby mode, coupling the reference clock signal to the delay line used in the delay-lock loop responsive to detecting the load mode command.

13. A method of operating a delay-lock loop included in a memory device, the method comprising:

in a standby mode of the memory device, isolating the reference clock signal from a delay line used in the delay-lock loop; and

in a normal operating mode of the memory device, continuously coupling the reference clock signal to the delay line for at least a predetermined period regardless of whether or not the memory device remains in the normal operating mode.

14. The method of claim 13, further comprising:

detecting when a bank of memory cells in the memory device becomes active when the memory device is in the standby mode;

coupling the reference clock signal to the delay line used in the delay-lock loop responsive to detecting that the bank of memory cells has become active.

15. The method of claim 13, further comprising:

determining if the delay-lock loop is in a locked condition when entering the standby mode;

if the determination is made that the delay-lock loop is in a locked condition when entering the standby mode, immediately isolating the reference clock signal from the delay line; and

if the determination is made that the delay-lock loop is not in a locked condition when entering the standby mode, continuing to couple the reference clock signal to the delay line for a predetermined period before isolating the reference clock signal from the delay line.

16. The method of claim 13, further comprising:

determining if the delay-lock loop is being reset when the memory device is in the standby mode; and

in response to determining that the delay-lock loop is being reset, coupling the reference clock signal to the delay line for a reset period before isolating the reference clock signal from the delay line, the reset period being longer than the predetermined period during which the reference clock signal is coupled to the delay line.

17. The method of claim 13, further comprising:

determining if memory device is transitioning from the standby mode to the normal operating mode; and

in response to determining that the memory device is transitioning from the standby mode to the normal operating mode, coupling the reference clock signal to the delay line for a period that is substantially longer than the predetermined period during which the reference clock signal is coupled to the delay line.

18. The method of claim 13 wherein the memory device is operable in a refresh mode in which refresh signals are generated internally in the memory device, and wherein the method further comprises:

determining if memory device is transitioning from the refresh mode in which refresh signals are generated internally in the memory device, and

in response to determining that the memory device is transitioning out of the refresh mode in which refresh signals are generated internally in the memory device, coupling the reference clock signal to the delay line for a period that is substantially longer than the predetermined period during which the reference clock signal is coupled to the delay line.

19. The method of claim 18 wherein the refresh mode in which refresh signals are generated internally in the memory device comprises a self-refresh mode.

20. The method of claim 13 wherein the delay-lock loop further comprise a phase detector having first and second input terminals receiving the reference clock signal and an output signal from the delay line, the phase detector being operable to generate an output signal that controls the delay of the delay line, the method further comprising selectively enabling and disabling the phase detector when the memory device is operating in the standby mode.

21. The method of claim 20 wherein the memory device is operable in an on die termination mode, and wherein the method further comprises disabling the phase detector in the on die termination mode while coupling the reference clock signal to the delay line when the memory device is operating in the standby mode.

22. The method of claim 13 wherein the memory device comprises a mode register that is programmable responsive to a load mode command, and wherein the method further comprises:

detecting the load mode command, and

when in the standby mode, coupling the reference clock signal to the delay line used in the delay-lock loop for at least the predetermined period responsive to detecting the load mode command.

23. In a memory device having a delay-lock loop including a delay line, a method of transitioning the memory device from a normal operating mode in which a reference clock signal is coupled to the delay line to a standby mode in which the reference clock signal is isolated from the delay line, the method comprising:

determining if the delay-lock loop is in a locked condition when entering the standby mode;

if the determination is made that the delay-lock loop is in a locked condition when entering the standby mode, immediately isolating the reference clock signal from the delay line; and

if the determination is made that the delay-lock loop is not in a locked condition when entering the standby mode, continuing to couple the reference clock signal to the delay line for a predetermined period before isolating the reference clock signal from the delay line.

24. The method of claim 23, further comprising:

detecting when a bank of memory cells in the memory device becomes active when the memory device is in the standby mode; and

coupling the reference clock signal to the delay line used in the delay-lock loop responsive to detecting that the bank of memory cells has become active.

25. The method of claim 23, further comprising:

determining if the delay-lock loop is being reset when the memory device is in the standby mode; and

in response to determining that the delay-lock loop is being reset, coupling the reference clock signal to the delay line for a reset period before isolating the reference clock signal from the delay line.

26. The method of claim 23, further comprising:

determining if memory device is transitioning from the standby mode to the normal operating mode; and

in response to determining that the memory device is transitioning from the standby mode to the normal operating mode, coupling the reference clock signal to the delay line for at least a predetermined period.

27. The method of claim 23 wherein the standby mode comprises a refresh mode in which refresh signals are generated internally in the memory device, and wherein the method further comprises:

determining if memory device is transitioning from a predetermined refresh mode; and

in response to determining that the memory device is transitioning out of the predetermined refresh mode, coupling the reference clock signal to the delay line for at least a predetermined period.

28. The method of claim 23 wherein the predetermined refresh mode comprises a self-refresh mode.

29. The method of claim 23 wherein the delay-lock loop further comprise a phase detector having first and second input terminals receiving the reference clock signal and an output signal from the delay line, the phase detector being operable to generate an output signal that controls the delay of the delay line, the method further comprising selectively enabling and disabling the phase detector when the memory device is operating in the standby mode.

30. The method of claim 29 wherein the memory device is operable in an on die termination mode, and wherein the method further comprises disabling the phase detector in the on die termination mode while coupling the reference clock signal to the delay line when the memory device is operating in the standby mode.

31. The method of claim 23 wherein the memory device comprises a mode register that is programmable responsive to a load mode command, and wherein the method further comprises:

detecting the load mode command, and

when in the standby mode, coupling the reference clock signal to the delay line used in the delay-lock loop responsive to detecting the load mode command.

32-59. -59. (canceled)