Network system

• US 20060251109A1
• Filed: 04/05/2005
• Published: 11/09/2006
• Est. Priority Date: 04/05/2005
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Wong, Michael, Muller, Shimon, Gajjar, Yatin, Hendel, Ariel, Puri, Rahoul, Lin, May
• Granted Patent: US 7,567,567 B2
• Time in Patent Office: Days
• US Class Current: 370/463
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/2441 relying on flow classification, e.g. using integrated services [IntServ]
• CPC Class Codes: H04L 47/283 in response to processing delays, e.g. caused by jitter or round trip time [RTT]
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 47/326 with random discard, e.g. random early discard [RED]
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9031 Wraparound memory, e.g. overrun or underrun detection
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal

Abstract

A network system which includes a plurality of processing entities, an interconnect device coupled to the plurality of processing entities, a memory system coupled to the interconnect device and the plurality of processing entities, a network interface unit coupled to the plurality of processing entities and the memory system via the interconnect device. The network interface includes a memory access module and a packet classifier. The memory access module includes a plurality of parallel memory access channels. The packet classifier provides a flexible association between packets and the plurality of processing entities via the plurality of memory access channels.

Claims

11. A network interface unit, the network interface unit coupling a network system with a network the network system having a plurality of processing entities, an interconnect device coupled to the plurality of processing entities and a memory system coupled to the interconnect device and the plurality of processing entities, the network interface unit comprising:

a memory access module, the memory access module including a plurality of parallel memory access channels,

a packet classifier, the packet classifier providing a flexible association between packets and the plurality of processing entities via the plurality of memory access channels.

12. The network interface unit of claim 11 wherein:

the packet classifier provides a hierarchical classification of packets received by the network system.

13. The network interface unit of claim 11 wherein:

the network interface unit performs a multilayer lookup operation on a packet.

15. The network interface unit of claim 11 wherein:

the plurality of memory access channels are associated with the plurality of processing entities to provide affinity.

16. The network interface unit of claim 11 wherein:

packets are moved within the network interface unit independently and in parallel to reduce packet movement system latency.

17. The network interface unit of claim 11 wherein:

the interconnect device enables relaxed ordering of information transfer.

18. The network interface unit of claim 11 wherein:

the plurality of memory access channels are virtualized and the network interface unit is shared among a plurality of domain environments.

19. A network interface unit, the network interface unit coupling a network system with a network the network system having a plurality of processing entities, an interconnect device coupled to the plurality of processing entities and a memory system coupled to the interconnect device and the plurality of processing entities, the network interface unit comprising:

a transmit memory access module, the transmit memory access module including a plurality of transmit memory access channels,

a receive memory access module, the receive memory access module including a plurality of receive memory access channels,

a access control module coupled to the transmit memory access module and the receive memory access module; and

,

a packet classifier coupled to the access control module, the packet classifier providing association between packets and the plurality of processing entities via the plurality of receive memory access channels.

1. A network system comprising:

a plurality of processing entities;

an interconnect device coupled to the plurality of processing entities;

a memory system coupled to the interconnect device and the plurality of processing entities;

a network interface unit coupled to the plurality of processing entities and the memory system via the interconnect device, the network interface including

a memory access module, the memory access module including a plurality of parallel memory access channels,

a packet classifier, the packet classifier providing a flexible association between packets and the plurality of processing entities via the plurality of memory access channels.

2. The network system of claim 1 further comprising:

a network system software stack executing on the network system.

3. The network system of claim 1 wherein:

the network system is scalable by adding additional processing entities.

4. The network system of claim 1 wherein:

the packet classifier provides a hierarchical classification of packets received by the network system.

5. The network system of claim 1 wherein:

the network interface unit performs a multilayer lookup operation on a packet.

6. The network system of claim 1 wherein:

the plurality of parallel memory access channels resolves any mutex contention experienced by packet movement.

7. The network system of claim 1 wherein:

the plurality of memory access channels are associated with the plurality of processing entities to provide affinity.

8. The network system of claim 1 wherein:

packets are moved within the network interface unit independently and in parallel to reduce packet movement system latency.

9. The network system of claim 1 wherein:

the interconnect device enables relaxed ordering of information transfer.

10. The network system of claim 1 wherein:

the plurality of memory access channels are virtualized and the network interface unit is shared among a plurality of domain environments.

14. The network interface unit of claim 1 I wherein:

the plurality of parallel memory access channels resolves any mutex contention experienced by packet movement.

20. The network interface unit of claim 19 further comprising:

a system interface module coupled to the transmit memory access module and the receive memory access module.

21. The network interface unit of claim 19 further comprising:

a transmit FIFO reorder logic module coupled between the access control module and the transmit memory access module.

22. The network interface unit of claim 21 wherein:

the transmit FIFO reorder logic module includes a transmit packet FIFO and a transmit reorder module.

23. The network interface unit of claim 19 wherein:

the receive packet FIFO module includes a receive packet FIFO and a receive control FIFO.

24. The network interface unit of claim 19 further comprising:

a plurality of programmable input output (PIO) registers, the plurality of PIO registers controlling the packet classifier.

22-1. The network interface unit of claim 19 further comprising:

a receive packet FIFO module coupled between the access control module and the receive memory access module.