Apparatus for and method of detection of powered devices over a network

• US 20060251158A1
• Filed: 02/16/2006
• Published: 11/09/2006
• Est. Priority Date: 05/03/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Millet, Guy, Cusnir, Pablo D., Wajcer, Daniel, Semel, Nohik, Sharon, Daniel, Isachar, Ori
• Granted Patent: US 7,564,904 B2
• Time in Patent Office: Days
• US Class Current: 375/219
• CPC Class Codes: H04L 41/12 Discovery or management of network topologies
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

A novel mechanism for detecting the presence of powered devices over a network. A unique, infinite pseudo-random sequence of pulses are generated and transmitted over the network to the link partner attached to the other end of the cable. At each time unit, the PSE decides whether or not to transmit a pulse at that time. Thus, the pulses generated have pseudo-random inter-pulse delays between them. In addition, each pulse is pseudo-randomly selected to have either positive or negative polarity. If the link partner is a powered device it will be in loopback mode and the transmitted pulses will be looped back to the transmitter (i.e. the PSE). The PSE, at each time unit regardless of whether or not a pulse was transmitted, opens a search window in which it listens to the RX line for the appropriate expected behavior. If a pulse was transmitted, the PSE expects to see a pulse looped back. Similarly, if no pulse was transmitted, the PSE does not expect to receive a signal during the search window. If the expected behavior is observed, a match counter is incremented, otherwise a mismatch counter is incremented. If a sufficient number of matches are received, the PSE concludes that a powered device is present on the network.

Claims

1. A method of detecting the presence of a powered device over a network, said method comprising the steps of:

transmitting over said network a random sequence of pulses having a sequence length, pseudo-random inter-pulse delay and a pseudo-random pulse polarity;

listening to said network for expected behavior at each time unit;

declaring a match if expected behavior is observed; and

declaring the presence of a powered device if a consecutive number of declared matches exceeds a threshold.

2. The method according to claim 1, wherein the step of declaring comprises the step of tolerating a configurable number of mismatches.

3. The method according to claim 1, wherein said sequence of pulses comprises an infinite pseudo-random pulse sequence.

4. The method according to claim 1, wherein said sequence of pulses comprises a sequence of Normal Link Pulses (NLPs).

5. The method according to claim 1, wherein said pseudo-random inter-pulse delay and said pseudo-random pulse polarity are determined in accordance with a coin-flipping algorithm whereby at each programmable period of time, it is randomly determined whether to transmit a pulse and if so, randomly determines the pulse polarity.

6. The method according to claim 1, wherein said step of listening comprises opening a search window for a finite duration of time in which it is expected to receive one pulse with correct polarity.

7. The method according to claim 1, further comprising the step of declaring a mismatch if a pulse or other energy is detected outside of a search window, wherein the number of allowed mismatches is configurable.

8. The method according to claim 1, further comprising the step of declaring failed detection if a pulse or other energy is detected outside of a search window.

9. The method according to claim 1, wherein said expected behavior comprises a received pulse matching the polarity of the transmitted pulse at a particular time unit.

10. The method according to claim 1, wherein said expected behavior comprises the absence of received signal in the event no pulse was transmitted at a particular time unit.

11. The method according to claim 1, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

12. The method according to claim 1, adapted to be implemented in a Field Programmable Gate Array (FPGA).

13. An apparatus for detecting the presence of a powered device over a network, comprising:

a pulse generator operative to transmit over said network a random sequence of pulses having a sequence length, pseudo-random inter-pulse delay and a pseudo-random pulse polarity;

a pulse detector operative to listen to said network for expected behavior at each time unit; and

a controller adapted to declare a match if expected behavior is observed and to declare the presence of a powered device if a consecutive number of declared matches exceeds a threshold.

14. The apparatus according to claim 13, wherein said controller comprises means for tolerating a configurable number of mismatches.

15. The apparatus according to claim 13, wherein said sequence of pulses comprises an infinite pseudo-random pulse sequence.

16. The apparatus according to claim 13, wherein said sequence of pulses comprises a sequence of Normal Link Pulses (NLPs).

17. The apparatus according to claim 13, wherein said pseudo-random inter-pulse delay and said pseudo-random pulse polarity are determined in accordance with a coin-flipping algorithm whereby at each programmable period of time, it is randomly determined whether to transmit a pulse and if so, randomly determines the pulse polarity.

18. The apparatus according to claim 13, wherein said pulse detector comprises means for opening a search window for a finite duration of time in which it is expected to receive one pulse with correct polarity.

19. The apparatus according to claim 13, further comprising means for declaring a mismatch if a pulse or other energy is detected outside of a search window, wherein the number of allowed mismatches is configurable.

20. The apparatus according to claim 13, further comprising means for declaring failed detection is if a pulse or other energy is detected outside of a search window.

21. The apparatus according to claim 13, further comprising a linear feedback shift register adapted to determine the timing of transmission of each pulse in said sequence.

22. The apparatus according to claim 13, further comprising a linear feedback shift register adapted to determine the polarity of each pulse in said sequence.

23. The apparatus according to claim 13, wherein said expected behavior comprises a received pulse matching the polarity of the transmitted pulse at a particular time unit.

24. The apparatus according to claim 13, wherein said expected behavior comprises the absence of received signal in the event no pulse was transmitted at a particular time unit.

25. The apparatus according to claim 13, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

26. The apparatus according to claim 13, adapted to be implemented in a Field Programmable Gate Array (FPGA).

27. A communications transceiver coupled to a communications channel, comprising:

a transmitter coupled to said communications channel;

a receiver coupled to said communications channel;

a powered device detector for detecting the presence of a powered device over said communications channel, comprising;

a pulse generator operative to transmit over said communications channel a random sequence of pulses having a sequence length, pseudo-random inter-pulse delay and a pseudo-random pulse polarity;

a pulse detector operative to listen to said communications channel for expected behavior at each time unit; and

a controller adapted to declare a match if expected behavior is observed and to declare the presence of a powered device if a consecutive number of declared matches exceeds a threshold.