Switching module

• US 20060251416A1
• Filed: 05/08/2006
• Published: 11/09/2006
• Est. Priority Date: 05/06/2005
• Status: Abandoned Application

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Inventors: Twigg, Kenneth R., Letner, Bernard J.
• Application Number:
  US11/429,218
• Publication Number:
  US 20060251416A1
• Time in Patent Office: Days
• US Class Current: 398/45
• CPC Class Codes: H04L 49/357 Fibre channel switches
• CPC Class Codes: H04L 49/55 Prevention, detection or correction of errors
• CPC Class Codes: H04L 49/555 Error detection

Abstract

Disclosed is a Mission Systems Network that may have an integrated core processor comprised of circuit card assemblies. The integrated core processor may include a fiber channel switching module with a trace buffer memory as an integral part of the module and contained within a common sealed enclosure. The trace buffer memory may be adapted to capture selected data traffic transiting the switch fabric based on pre-selected triggers. The selected data can be read out of the trace buffer memory and used for selected diagnostics.

Claims

1. A network system comprising:

at least one multi-port channel switching module for a fiber optic network;

a trace buffer memory physically integrated with said switching module and housed in an enclosure; and

one or more controllers in said enclosure, said one or more controllers adapted to cause selected portions of information to be stored in the trace buffer memory, the selected information being selected according to one or more predetermined trigger options, the selected information being selected from data transiting the switching module from other modules in the enclosure through an optical backplane.

2. The network system of claim 1, wherein said trigger options are based at least in part on the identity of a source port and a destination port.

3. The network system of claim 2, wherein said trigger option includes a pre-trigger option, a mid-trigger option and a post-trigger option.

4. The network system of claim 3, wherein said monitored information is time stamped.

5. The network system of claim 3, wherein said stored selected portions include only headers of said monitored information.

6. The network system of claim 5, wherein said stored selected portions include only payload of said monitored information.

7. The network system of claim 5, wherein said stored selected portions include headers and payload of said monitored information.

8. The network system of claim 1, including at least one means for accessing and analyzing said monitored information.

9. The network system of claim 8, wherein said trace buffer memory is on said module and integrated with a switch fabric of said module.

10. The network system of claim 9, wherein said system is adapted for hardware and software diagnostics and debugging.

11. The network system of claim 10, wherein said at least one enclosure is an aircraft and said network system is also housed in said at least one enclosure.

12. The network system of claim 10, wherein said at least one enclosure comprises a rack with slots dimensioned for receiving the other modules adapted for communication via a backplane.

13. The network system of claim 12, wherein said at least one enclosure is sealed.

14. The network system of claim 13, wherein said means is external to said enclosure.

15. The network system of claim 13, wherein said means is inside of said enclosure.

16. A line replaceable module adapted for installation in an integrated core processor rack comprising:

a substrate;

a switch fabric supported by the substrate and adapted to handle data traffic between nodes external to the line replaceable module in the integrated core processor rack; and

a trace buffer memory supported by the substrate and adapted selectively to record communications transiting the switch fabric.

17. A method for analyzing data captured on an aircraft, the method comprising:

providing a trace buffer memory on a line replaceable module and coupled to an optical backplane of an integrated core processor rack installed on the aircraft;

providing a trace buffer memory controller on the line replaceable module;

programming the trace buffer memory controller with triggers to cause the trace buffer memory to capture selected data from data flowing through the optical backplane;

providing access to the captured data;

providing means to offload automatically the captured data when preselected criteria are met; and

analyzing the offloaded data with a data analyzer.

18. The method of claim 17, wherein the preselected criteria comprise the trace buffer memory approaching capacity.