Integrated circuit on high performance chip

• US 20060252229A1
• Filed: 06/23/2004
• Published: 11/09/2006
• Est. Priority Date: 06/24/2003
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Original Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Inventors: Ulmer, Laurent, Parat, Guy, Joly, Jean-Pierre
• Granted Patent: US 8,048,766 B2
• Time in Patent Office: Days
• US Class Current: 438/455
• CPC Class Codes: B81C 1/00253 Processes for integrating an electronic processing unit with a micromechanical structure not provided for in B81C1/0023 - B81C1/00246
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of fabricating a die containing an integrated circuit, including active components and passive components, includes producing a first substrate containing at least one active component of active components and a second substrate containing critical components of the passive components, such as perovskites or MEMS, and bonding the two substrates by a layer transfer. The method provides an improved monolithic integration of devices such as MEMS with transistors.

Claims

15. A die fabricated by a method according to 13.

16. A die containing an integrated circuit comprising active components and passive components and including a single stack of layers, whereinsaid die comprises an interface between two of said layers such that a said first portion of the die situated on one side of said interface contains at least one active component of said active components and a second said portion of said die contains “

critical”

components of said passive components.

1. A method of fabricating a die containing an integrated circuit comprising active components and passive components, the method comprising:

producing a first substrate containing at least one active component and a second substrate containing critical passive components; and

bonding the two substrates, wherein the bonding comprises performing a layer transfer through molecular adhesion.

2. A method according to claim 1 wherein said at least one active component comprises transistors.

3. A method according to claim 1 wherein said critical passive components comprise at least one capacitor and at least one microelectromechanical system (MEMS).

4. A method according to claim 1 wherein said critical passive components comprise at least one of one capacitor or at least one microelectromechanical system (MEMS).

5. A method according to claim 3 wherein a dielectric material of said at least one capacitor comprises is a perovskite.

6. A method according to claim 1 wherein producing said second substrate comprises producing an electrically conductive material.

7. A method according to claim 1 wherein producing said second substrate comprises producing a dielectric material.

8. A method according to claim 7 wherein producing said second substrate comprises producing perovskite.

9. A method according to claim 8 further comprising producing dielectric insulation trenches in said second substrate during the production of said second substrate.

10. A method according to claim 9 further comprising producing at least one non-critical passive component during the production of said second substrate.

11. A method according to claim 9 wherein producing the non-critical passive component comprises producing a capacitor in trenches.

12. A method according to claim 9 further comprising producing at least one inductor in the vicinity of the a face of the second substrate opposite a bonding face after said bonding of the two substrates.

13. A method according to claim 12 further comprising producing said at least one inductor produced on said inductive insulation trenches previously produced in said second substrate.

14. A method according to claim 12 further comprising producing at least one interconnection line passing through all or part of the second substrate after said bonding of said first and second substrates.

17. A die according to claim 16 wherein said critical passive components comprise at least one capacitor and at least one MEMS enclosed in a cavity situated inside said die.

18. A die according to claim 16 wherein said critical passive components comprise at least one capacitor or at least one MEMS enclosed in a cavity situated inside said die.

19. A die according to claim 17 wherein the capacitor comprises a dielectric material comprising perovskite.

20. A die according to claim 17 said die further comprises dielectric insulation trenches.

21. A die according to claim 18 wherein said integrated circuit further comprises at least one non-critical passive component

22. A die according to claim 21 wherein said non-critical passive component comprises a capacitor in trenches.

23. A die according to claim 18 wherein said active components are disposed in the vicinity of a first face of the die and wherein said integrated circuit further comprises at least one inductor situated in a vicinity of said face of the die opposite said first face.

24. A die according to claim 22 wherein said at least one inductor is situated on inductive insulation trenches.

25. A die according to any one of claim 21 wherein said active components are disposed in a vicinity of a first face of said die (100) and said die further comprises at least one interconnection line that emerges in the vicinity of said face of said die opposite said first face.

25-1. A die according to any one of claim 21 wherein said active components are disposed in a vicinity of a first face of said die (100) and said die further comprises at least one interconnection line that emerges in the vicinity of said face of said die opposite said first face.