Semiconductor structures having via structures between planar frontside and backside surfaces and methods of fabricating the same

• US 20060252262A1
• Filed: 05/03/2005
• Published: 11/09/2006
• Est. Priority Date: 05/03/2005
• Status: Abandoned Application

• Current Assignee: Teledyne Licensing, LLC
• Original Assignee: Rockwell Scientific Licensing LLC
• Inventors: Kazemi, Hooman
• Application Number:
  US11/121,504
• Publication Number:
  US 20060252262A1
• Time in Patent Office: Days
• US Class Current: 438/667
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate

Abstract

Methods of backside planarization processes have been developed to gain a high resolution backside process lithography and to make possible the development of dual faced MMICs and circuits. Two different processes have been employed to planarize via structures of various depths, one including epoxy-fill via structures with depths of 10 mils and the other solid-metal via structures with depths of 3.5 mils. Application of a wafer fabricated using methods of the present invention has been demonstrated in a monolithic circuit, where bias control to the frontside of the wafer was established by solder bumps on the planarized backside surface of a wafer including epoxy-filled via structures.

Claims

1. A method of forming a semiconductor structure comprising:

forming vias through a semiconductor substrate having a frontside surface and a backside surface;

depositing conductive material in the vias to establish a conductive path between the frontside surface and the backside surface;

filling the vias with a core material; and

removing portions of the conductive material and the core material so the backside surface of the substrate is substantially planar with respect to the conductive material and the core material.

2. The method of claim 1 wherein the vias have sidewalls and depositing conductive material in the vias comprises depositing a layer of conductive material on the sidewalls.

3. The method of claim 2 wherein depositing a layer of conductive material on the sidewalls comprises:

depositing a seed layer on the sidewalls; and

depositing the conductive material on the seed layer.

4. The method of claim 3 wherein the seed layer is deposited on the sidewalls by sputtering.

5. The method of claim 3 wherein the conductive material is deposited on the seed layer using a plating process.

6. The method of claim 2 further comprising depositing a layer of conductive material across the openings of the vias adjacent the frontside surface of the substrate.

7. The method of claim 6 wherein the layer of conductive material is deposited across the openings of the vias by:

depositing a metallization pad on the frontside surface prior to forming the vias; and

depositing the layer of conductive material on the portions of the metallization pad exposed by the vias.

8. The method of claim 7 wherein the layer of conductive material is deposited on the exposed portions of the metallization pad by:

depositing a seed layer on the exposed portions of the metallization pad; and

depositing the conductive material on the seed layer.

9. The method of claim 8 wherein the seed layer is deposited on the metallization pad by sputtering.

10. The method of claim 8 wherein the conductive material is deposited on the seed layer using a plating process.

11. The method of claim 1 wherein filling the vias with a core material comprises applying a material on the backside surface to fill the vias.

12. The method of claim 11 wherein the material is conductive.

13. The method of claim 11 wherein the material is non-conductive.

14. The method of claim 11 further comprising out gassing the material to form a core structure that is substantially void of air pockets.

15. The method of claim 11 further comprising curing the material.

16. The method of claim 1 wherein portions of the conductive material and the core material are removed by lapping.

17. A method of forming a semiconductor structure comprising:

forming vias through a semiconductor substrate having a frontside surface and a backside surface;

filling the vias with material, including at least partially with a conductive material to establish a conductive path between the frontside surface and the backside surface; and

removing portions of the conductive material so the backside surface of the substrate is substantially planar with respect to the conductive material.

18. The method of claim 17 wherein the via has a frontside opening and a backside opening and filling the vias with conductive material comprises depositing conductive material in the via until the conductive material reaches at least the backside opening.

19. The method of claim 18 wherein depositing conductive material in the via comprises:

depositing a metallization pad on the frontside surface prior to forming the vias; and

depositing layers of conductive material on the portions of the metallization pad exposed by the vias.

20. The method of claim 19 wherein the conductive material is deposited on the metallization pad using a plating process.

21. The method of claim 18 wherein depositing conductive material in the via comprises applying a conductive material on the backside surface and allowing it to fill the vias.

22. The method of claim 21 further comprising out gassing the conductive material to remove substantially all air pockets.

23. The method of claim 21 further comprising curing the conductive material.

24. The method of claim 17 wherein portions of the conductive material are removed by lapping.

25. A semiconductor structure comprising:

a substrate having a frontside surface and a substantially planar backside surface; and

a plurality of via structures through the substrate, having an electrically conductive frontside structure forming part of the frontside surface, and an electrically conductive core structure electrically connected with the frontside structure and including a backside structure forming part of the backside surface.

26. The structure of claim 25 wherein the frontside structure comprises a layer of conductive material.

27. The structure of claim 26 wherein the layer of conductive material is a solid layer across the cross section of the via structures.

28. The structure of claim 26 wherein the layer of conductive material comprises a first layer of conductive material different from a second layer of conductive material.

29. The structure of claim 28 wherein the first layer of conductive material is capable of having the second layer of conductive material deposited thereon using a plating process.

30. The structure of claim 25 wherein the core structure comprises a core material at least partially surrounded by an electrically conductive through-element electrically connected to the frontside structure, parts of the core material and the through-element forming part of the backside structure.

31. The structure of claim 30 wherein the via structure includes at least one sidewall surface and the through-element comprises a layer of conductive material on the sidewall surface.

32. The structure of claim 31 wherein the layer of conductive material comprises a first layer of conductive material different from a second layer of conductive material.

33. The structure of claim 32 wherein the first layer of conductive material is capable of having the second layer of conductive material deposited thereon using a plating process.

34. The structure of claim 30 wherein the through-element encircles the core material and the part of the through-element forming part of the backside structure is an electrically conductive ring.

35. The structure of claim 30 wherein the core material is capable of being mechanically applied to the wafer.

36. The structure of claim 30 wherein the core material is conductive.

37. The structure of claim 30 wherein the core material is non-conductive.

38. The structure of claim 30 wherein the core material is substantially void of air pockets.

39. The structure of claim 25 wherein the core structure comprises a conductive material electrically connected to the frontside structure, part of the conductive material forming part of the backside structure.

40. The structure of claim 39 wherein the frontside structure is formed of a material capable of having the conductive material deposited thereon using a plating process.

41. The structure of claim 39 wherein the conductive material is substantially void of air pockets.

42. The structure of claim 25 wherein the frontside structure and the core structure are the same structure.

43. The structure of claim 42 wherein the same structure is formed of a conductive material that is capable of being mechanically applied to the substrate.

44. A semiconductor structure comprising:

a substrate having a frontside surface and a substantially planar backside surface; and

a plurality of vias through the substrate, the vias filled with a via material, including at least partially with a conductive material to establish a conductive path between the frontside surface and the backside surface, the backside surface of the substrate being substantially planar with respect to the via material.

45. The structure of claim 44 wherein the conductive material is plated metal.

46. The structure of claim 45 wherein the remainder of the via material is conductive.

47. The structure of claim 46 wherein the remainder of the via material is non-conductive.

48. The structure of claim 44 wherein the conductive material is a liquid-based material.

49. The structure of claim 44 wherein the via material is plated metal.

50. The structure of claim 44 wherein the via material is a conductive liquid-based material.