System and method for providing bradycardia therapy by implantable device in presence of system faults

• US 20060253009A1
• Filed: 05/05/2005
• Published: 11/09/2006
• Est. Priority Date: 05/05/2005
• Status: Active Grant

• Current Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Original Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Inventors: Hoyme, Kenneth P., Linder, William J., Elliott, Lynn S., Doshi, Hiten J., Stubbs, Scott, Sowder, Conrad L.
• Granted Patent: US 7,363,080 B2
• Time in Patent Office: Days
• US Class Current: 600/323
• CPC Class Codes: A61N 1/362 Heart stimulators heart defibrillators A61N1/39
• CPC Class Codes: A61N 1/3684 for stimulating the heart at multiple sites of the ventricle or the atrium
• CPC Class Codes: A61N 1/36842 Multi-site stimulation in the same chamber
• CPC Class Codes: A61N 1/36843 Bi-ventricular stimulation

Abstract

A system and method is disclosed by which an implantable cardiac device may deliver bradycardia therapy in the event of a system fault. A hardware-based safety core provides the logic circuitry for delivering bradycardia therapy in the form of synchronous pacing in the event of a fault which disables operation of the device'"'"'s primary control circuitry. The safety core pacemaker eliminates common mode failure of the primary control circuits used in the primary pacing system. Failures in the primary controller memory or execution will activate the safety core pacemaker.

Claims

1. A system for providing bradycardia therapy in the presence of a system fault, comprising:

a ventricular sensing circuit;

a pacing pulse generator;

a primary controller for controlling the operation of the pacing pulse generator in accordance with a programmed pacing mode;

fault monitoring circuitry;

a safety core pacemaker which is activated upon detection of a system fault which initiates a system reset and halts the primary controller;

wherein the safety core pacemaker is a hardware-based logic circuit which comprises an escape interval timer which upon expiration causes the pacing pulse generator to deliver a ventricular pacing pulse and which is reset by a ventricular pace or sense.

2. The system of claim 1 wherein the primary controller is halted when a fault is detected.

3. The system of claim 1 wherein the safety core pacemaker is configured using hardware-based logic as a VVI pacemaker which is enabled with each system reset.

4. The system of claim 3 the safety core pacemaker is configurable to pace either the right or left ventricle only or may deliver biventricular pacing (e.g., with a minimum offset between the right and left ventricular paces).

5. The system of claim 3 wherein, during a system reset, the safety core pacemaker is configured to use sense signals generated by the right ventricular sensing circuit in order to control pacing.

6. The system of claim 5 wherein the escape interval timer is reset by either an RV pacing output or an RV sense signal.

7. The system of claim 3 wherein the safety core also has the capability of delivering shock therapy and wherein a post-shock delay signal generated when a defibrillation shock is delivered is used to inhibit pacing for a preset time.

8. The system of claim 1 wherein the primary controller disables the safety core pacemaker when the primary controller successfully completes its reset sequence.

9. The system of claim 8 wherein the safety core pacemaker operates in parallel to the primary controller using an escape interval set to the maximum pacing interval that is allowed for the system when the safety core pacemaker is disabled by the primary controller.

10. The system of claim 8 wherein, if the escape timer expires while the primary controller and safety core pacemaker are operating in parallel, paces are delivered to both ventricles and a system reset is performed.

11. The system of claim 1 further comprising a keyed control register to allow the primary controller to disable the safety core pacemaker in order to prevent therapy competition.

12. The system of claim 1 further comprising non-volatile register to provide a priority disable for the safety core pacemaker.

13. The system of claim 1 further comprising a reset controller for managing a reset process after detection of a fault by the fault monitoring circuitry.

14. The system of claim 13 wherein, upon detection of a fault, the reset controller is configured to signal the primary controller to halt operation and to activate the safety core pacemaker.

15. The system of claim 14 wherein, upon detection of a fault, the reset controller is configured to signal the primary controller to validate its operation with a self-test and to deactivate the safety core pacemaker if the primary controller is validated.

16. The system of claim 1 wherein the fault monitoring circuitry includes a watchdog timer.

17. The system of claim 1 wherein the fault monitoring circuitry includes a clock deviation monitor.

18. The system of claim 1 wherein the fault monitoring circuitry includes circuitry for detecting memory errors.

19. The system of claim 13 wherein, upon detection of a fault, a pending reset signal is raised by the reset controller to initiate logging of the cause of the pending reset by the primary controller.

20. The system of claim 1 further comprising a system-reset monitor for detecting system resets caused by non-recoverable and persistent faults.