FPGA emulation system

• US 20060253762A1
• Filed: 03/14/2006
• Published: 11/09/2006
• Est. Priority Date: 03/16/2005
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Schalick, Christopher A.
• Granted Patent: US 8,000,954 B2
• Time in Patent Office: Days
• US Class Current: 714/742
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

This invention features an FPGA emulation system including an FPGA device under test having a plurality of pins. A bus functional model circuit responsive to signals representing predetermined input characteristics of the FPGA device under test and configured to apply one or more signals to the FPGA device under test corresponding to the predetermined input characteristics and configured to receive one or more signals representing output characteristics of the FPGA device under test to emulate the operation of the FPGA device under test in a predefined selectable and flexible electrical operating environment. This invention also features an FPGA emulation system including an FPGA device under test having at least one component and a plurality of pins operating in a predetermined native target environment, a bus functional model engine for simulating and capturing output characteristics of the at least one component of the FPGA device under test and simulating and releasing input characteristics of the at least one component of the FPGA device under test, and a bus functional model circuit embedded in the FPGA device under test configured to receive one or more signals representing the input characteristics of the at least one component and configured to release one or more signals representing the output characteristics of the at least one component such that the bus functional model engine emulates the operation of the at least one component of the FPGA device under test in the predetermined native target environment.

Claims

1. An FPGA emulation system comprising:

an FPGA device under test having a plurality of pins; and

a bus functional model circuit responsive to signals representing predetermined input characteristics of said FPGA device under test and configured to apply one or more signals to said FPGA device under test corresponding to said predetermined input characteristics and configured to receive one or more signals representing output characteristics of said FPGA device under test to emulate the operation of said FPGA device under test in a predefined selectable and flexible electrical operating environment.

2. The system of claim 1 further including a bus functional model engine for simulating and capturing said predetermined input characteristics and simulating and releasing said output characteristics.

3. The system of claim 2 in which said bus functional model engine emulates the operation of said FPGA device under test in the predefined selectable and flexible electrical operating environment.

4. The system of claim 1 in which said bus functional model circuit is configured to apply at least one test operation to said FPGA device under test and emulate the results of said at least one test operation in said predefined selectable and flexible electrical operating environment.

5. The system of claim 1 in which said bus functional model circuit includes a plurality of pins.

6. The system of claim 5 in which said bus functional model circuit is coupled to said FPGA device under test.

7. The system of claim 6 in which each pin of selected pins of said FPGA device under test is coupled to a corresponding pin type of said bus functional model circuit.

8. The system of claim 6 further including protective circuitry coupled between said FPGA device under test and said bus functional model circuit.

9. The system of claim 1 in which said bus functional model circuit and said FPGA device under test are chosen to have similar electrical properties and functions.

10. The system of claim 1 in which said one or more signals applied to said FPGA device under test include one or more signals chosen from the group consisting of:

power supply signals, timing reference signals, impedance reference signals, and signals representing said predetermined input characteristics.

11. The system of claim 1 further including a controller circuit responsive to said predetermined input characteristics and commands that select one or more of at least one programmable power supply, at least one programmable oscillator circuit, at least one programmable impedance reference device, and at least one programmable timing reference device to define said predefined selectable and flexible electrical operating environment.

12. The system of claim 11 in which said at least one programmable impedance reference device provides one or more impedance reference signals to said bus functional model circuit and said FPGA device under test.

13. The system of claim 11 in which said at least one programmable timing reference device provides one or more timing reference signals to said bus functional model circuit and said FPGA device under test.

14. The system of claim 11 in which said bus functional model circuit, said FPGA device under test, said controller circuit, said at least one programmable power supply, said at least one programmable oscillator circuit, said at least one programmable impedance reference device, and said at least one programmable timing reference device are disposed on a removable device.

15. The system of claim 14 in which said removable device is integrated with a computer system.

16. The system of claim 15 further including a conversion circuit for converting said predetermined input characteristics to electrical control signals and said output characteristics to software signals.

17. The system of claim 16 in which said electrical control signals enable said bus functional model circuit.

18. The system of claim 16 in which said electrical control signals enable one or more of said at least one programmable power supply, said at least one programmable oscillator circuit, said at least one programmable impedance reference device, and a said at least one programmable timing reference device.

19. The system of claim 1 further including a logic simulator coupled to said bus functional model engine for receiving simulated inputs and transmitting simulated outputs.

20. An FPGA emulation system comprising:

a bus functional model circuit responsive to signals representing predetermined input characteristics of an FPGA device under test and configured to apply one or more signals to said FPGA device under test corresponding to said predetermined input characteristics and configured to receive one or more signals representing output characteristics of said FPGA device under test to emulate the operation of said FPGA device under test in a predefined selectable and flexible electrical operating environment.

21. An FPGA emulation system comprising:

an FPGA device under test having a plurality of pins;

a bus functional model engine for simulating and capturing predetermined input characteristics of said FPGA device under test and simulating and releasing output characteristics of said FPGA device under test; and

a bus functional model circuit responsive to signals representing said predetermined input characteristics configured to apply one or more signals to said FPGA device under test corresponding to said predetermined input characteristics and configured to receive one or more signals representing output characteristics of said FPGA device under test such that said bus functional model engine emulates the operation of said FPGA device under test in a predefined selectable and flexible electrical operating environment.

22. The system of claim 21 in which said bus functional model circuit is configured to apply at least one test operation to said FPGA device under test and emulate the results of said at least one test operation in said predefined selectable and flexible electrical operating environment.

23. The system of claim 21 in which said bus functional model circuit includes a plurality of pins.

24. The system of claim 23 in which said bus functional model circuit is coupled to said FPGA device under test.

25. The system of claim 24 in which each pin, or selected pins, of said FPGA device under test is coupled to a corresponding pin type of said bus functional model circuit.

26. The system of claim 24 further including protective circuitry coupled between said FPGA device under test and said bus functional model circuit.

27. The system of claim 21 in which said bus functional model circuit and said FPGA device under test are chosen to have similar electrical properties and functions.

28. The system of claim 21 in which said one or more signals applied to said FPGA device under test include one or more signals chosen from the group consisting of:

power supply signals, timing reference signals, impedance reference signals, and signals representing said predetermined input characteristics.

29. The system of claim 21 further including a controller circuit responsive to said predetermined input characteristics and commands that select one or more of at least one programmable power supply, at least one programmable oscillator circuit, at least one programmable impedance reference device, and at least one programmable timing reference device to define said predefined selectable and flexible electrical operating environment.

30. The system of claim 29 in which said at least one programmable impedance reference device provides one or more impedance reference signals to said bus functional model circuit and said FPGA device under test.

31. The system of claim 29 in which said at least one programmable timing reference device provides one or more timing reference signals to said bus functional model circuit and said FPGA device under test.

32. The system of claim 29 in which said at least one programmable power supply, said at least one programmable oscillator circuit, said at least one programmable impedance reference device, and a said at least one programmable timing reference device are disposed on a removable device.

33. The system of claim 32 in which said removable device is integrated with a computer system.

34. The system of claim 33 further including a conversion circuit for converting said predetermined input characteristics to electrical control signals and said output characteristics to software signals.

35. The system of claim 34 in which said electrical control signals enable said bus functional model circuit.

36. The system of claim 35 in which said electrical control signals enable one or more of said at least one programmable power supply, said at least one programmable oscillator circuit, said at least one programmable impedance reference device, and said at least one programmable timing reference device.

37. The system of claim 21 further including a logic simulator coupled to said bus functional model engine for receiving simulated inputs and transmitting simulated outputs.

38. An FPGA emulation system comprising:

a bus functional model engine for simulating and capturing predetermined input characteristics of an FPGA device under test and simulating and releasing output characteristics of said FPGA device under test; and

a bus functional model circuit responsive to signals representing said predetermined input characteristics configured to apply one or more signals to said FPGA device under test corresponding to said predetermined input characteristics of said FPGA device under test such that said bus functional model engine emulates the operation of said FPGA device under test in a predefined selectable and flexible electrical operating environment.

39. An FPGA emulation system comprising:

an FPGA device under test having a plurality of pins;

a bus functional model circuit having a plurality pins;

a connector coupling the FPGA device under test to the bus functional model circuit; and

wherein the bus functional model circuit is programmed to input signals into said FPGA device under test and to receive output signals from said FPGA device under test to more accurately emulate the operation of said FPGA device under test in a predefined selectable and flexible electrical operating environment.

40. The system of claim 39 in which said bus functional model circuit is configured to apply at least one test to said FPGA device under test in said predefined selectable and flexible electrical operating environment and emulate the results of said at least one test.

41. The system of claim 39 in which each pin, or selected pins, of said FPGA device under test is coupled to a corresponding pin type of said bus functional model circuit.

42. The system of claim 39 further including protective circuitry coupled between the pins of said FPGA device under test and said bus functional model circuit.

43. An FPGA emulation system comprising:

an FPGA device under test having at least one component and a plurality of pins operating in a predetermined native target environment;

a bus functional model engine for simulating and capturing output characteristics of said at least one component of said FPGA device under test and simulating and releasing input characteristics of said at least one component of said FPGA device under test; and

a bus functional model circuit embedded in said FPGA device under test configured to receive one or more signals representing said input characteristics of said at least one component and configured to release one or more signals representing said output characteristics of said at least one component such that said bus functional model engine emulates the operation of said at least one component of said FPGA device under test in said predetermined native target environment.

44. The system of claim 43 further including a component model engine responsive to said input characteristics for generating said output characteristics of said at least one component.

45. The system of claim 43 in which said bus functional model circuit is configured to apply at least one test operation from said at least one component of said FPGA device under test and emulate the results of said at least one test operation in said predetermined native target environment.

46. The system of claim 43 further including a conversion circuit for converting said output characteristics to electrical or hardware signals and said input characteristics to software signals.

47. The system of claim 46 further including a controller circuit responsive to said electrical signals for enabling said bus functional model circuit.

48. The system of claim 46 further including a programming cable coupled between said conversion circuit and said FPGA device under test.

49. The system of claim 43 in which said bus functional model engine simulates and captures output characteristics of a plurality of components of said FPGA device under test and simulates and releases the input characteristics of said plurality of components of said FPGA device under test.

50. The system of claim 49 in which said bus functional model circuit is configured to receive signals destined for said plurality of components of said FPGA device under test corresponding to input characteristics of said plurality of components of said FPGA device under test and configured to apply signals representing output characteristics of said plurality of components of said FPGA device under test such that said bus functional model engine emulates the operation of said plurality of components of said FPGA device under test in said predetermined native target environment.

51. The system of claim 43 in which said bus functional model engine simulates and captures output characteristics of all the components of said FPGA device under test and simulates and releases the input characteristics of all the components of said FPGA device under test.

52. The system of claim 49 in which said bus functional model circuit is configured to receive signals destined for said all the components of said FPGA device under test corresponding to input characteristics of all the components of said FPGA device under test and configured to apply signals representing output characteristics of all the components of said FPGA device under test such that said bus functional model engine emulates the operation of said all the components of said FPGA device under test in said predetermined native target environment.

53. The system of claim 43 further including a logic simulator coupled to said bus functional model engine for receiving simulated inputs and transmitting simulated outputs.

54. An FPGA emulation system comprising:

an FPGA device under test having at least one component and a plurality of pins operating in a predetermined native target environment;

a bus functional model engine for simulating and capturing output characteristics of said at least one component of said FPGA device under test and simulating and releasing output characteristics of said at least one component of said FPGA device under test;

a bus functional model circuit embedded in said FPGA device under test configured to receive one or more signals corresponding to said input characteristics of said at least one component and configured to release one or more signals representing said output characteristics of said at least one component such that said bus functional model engine emulates the operation of said at least one component of said FPGA device under test in said predetermined native target environment; and

a component model engine responsive to said input characteristics for generating said output characteristics of said at least one component.

55. An FPGA emulation system comprising:

an FPGA device under test having at least one component and a plurality of pins;

a first bus functional model engine for simulating and capturing input characteristics of said FPGA device under test and simulating and releasing output characteristics of said FPGA device under test;

a first bus functional model circuit responsive to signals representing said input characteristics configured to apply one or more signals to said FPGA device under test corresponding to said input characteristics of said FPGA device under test and configured to receive one or more signals representing output characteristics of said FPGA device under test such that said bus functional model engine emulates the operation of said FPGA device under test in a predefined selectable and flexible electrical operating environment;

a second bus functional model engine for simulating and capturing output characteristics of said at least one component of said FPGA device under test and simulating and releasing input characteristics of said at least one component of said FPGA device under test; and

at least one additional bus functional model circuit embedded in said FPGA device under test configured to receive one or more signals corresponding to said input characteristics of said at least one component and configured to release one or more signals representing said output characteristics of said at least one component such that said at least one additional bus functional model engine emulates the operation of said at least one component of said FPGA device under test in said predefined selectable and flexible electrical operating environment

56. The system of claim 55 further including a component model engine responsive to said input characteristics of said at least one component provided by said at least one additional bus functional model circuit for generating said output characteristics of said at least one component.