High-voltage semiconductor device and method of manufacturing the same

• US 20060255369A1
• Filed: 05/09/2006
• Published: 11/16/2006
• Est. Priority Date: 05/13/2005
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Joon-Hyung, Kim, Yong-Chan, Kim, Yong-Don
• Application Number:
  US11/430,580
• Publication Number:
  US 20060255369A1
• Time in Patent Office: Days
• US Class Current: 257/219
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence

Abstract

A high-voltage semiconductor device and a method of manufacturing the high-voltage semiconductor device are provided. For example, with the above device and method drift regions having first depths are formed in a semiconductor substrate by doping first impurities. The drift regions are spaced apart from each other to define a channel region between the drift regions. Source/drain regions having second depths are formed at first portions of the drift regions by doping second impurities. Impurity accumulation regions having third depths are formed at second portions of the drift region adjacent to the source/drain regions by doping third impurities. A gate insulation layer pattern is formed on the semiconductor substrate to partially expose the source/drain regions. A gate conductive layer pattern is formed on a portion of the gate insulation layer pattern where the channel region is positioned. A buffer layer capable of preventing a rapid increase of a current is formed on the gate structure and the gate insulation layer pattern.

Claims

1. A high-voltage semiconductor device comprising:

a semiconductor substrate;

a plurality of drift regions formed in the semiconductor substrate, each of the plurality of drift regions formed having a first impurity, a first impurity concentration and a first depth, wherein the drift regions are separate from each other to define a channel region between the drift regions;

a source region and a drain region formed at first portions of the drift regions, the source region and the drain region formed each having a second impurity, a second impurity concentration and a second depth, wherein the second depths of the source/drain regions are substantially smaller than the first depths;

a plurality of impurity accumulation regions formed at second portions of the drift regions adjacent to the source/drain regions, each of the plurality of impurity accumulation regions formed having a third impurity, a third impurity concentration and a third depth, wherein the thirds depths of the impurity accumulation regions are substantially smaller than the first depths,;

a gate structure formed on the semiconductor substrate, wherein the gate structure comprises a gate insulation layer pattern formed on the semiconductor substrate to partially expose the source/drain regions, and a gate conductive layer pattern formed on a portion of the gate insulation layer pattern where the channel region is positioned; and

a buffer layer formed on the gate structure.

2. The high-voltage semiconductor device of claim 1, wherein the semiconductor device further comprises an isolation layer for dividing the semiconductor substrate into an active region and a field region, wherein the channel region, the drift regions and the gate structure are positioned on the active region.

3. The high-voltage semiconductor device of claim 1, wherein the first, the second and the third impurities comprise substantially the same elements.

4. The high-voltage semiconductor device of claim 3, wherein the first, the second and the third impurities comprise elements in Group III.

5. The high-voltage semiconductor device of claim 3, wherein the first, the second and the third impurities comprise elements in Group V.

6. The high-voltage semiconductor device of claim 1, wherein the second impurity concentrations are substantially larger than the third impurity concentrations, and the third impurity concentrations are substantially larger than the first impurity concentrations.

7. The high-voltage semiconductor device of claim 1, wherein the second depths are substantially larger than the third depths.

8. The high-voltage semiconductor device of claim 1, wherein the source/drain regions are spaced apart from the channel region.

9. The high-voltage semiconductor device of claim 1, wherein the impurity accumulation regions are adjacent to the source/drain regions whereas the impurity accumulation regions are spaced apart from the channel region.

10. The high-voltage semiconductor device of claim 1, wherein the gate insulation layer pattern comprises silicon oxide or metal oxide layer, the gate conductive layer pattern comprises metal, metal nitride or polysilicon doped with impurities, and the buffer layer comprises silicon nitride or silicon oxynitride.

11. The high-voltage semiconductor device of claim 1, further comprising a deep well region formed in the semiconductor substrate to enclose the channel region and the drift regions, the well region having a fourth impurity which is different from the first impurities and a fourth impurity concentration substantially smaller than the first impurity concentrations, wherein the deep well region has a fourth depth substantially larger than the first depth.

12. A method of manufacturing a high-voltage semiconductor device, the method comprising:

forming a plurality of drift regions in a semiconductor substrate by doping first impurities with first impurity concentrations into the semiconductor substrate, such that each of the plurality of drift regions formed have a first impurity, a first impurity concentration and a first depth, and wherein the drift regions are spaced apart from each other to define a channel region between the drift regions;

forming a source region and a drain region at first portions of the drift regions by doping second impurities with second impurity concentrations into the first portions of the drift regions such that the source region and the drain region formed each have a second impurity, a second impurity concentration and a second depth, and wherein the second depths of the source/drain regions are substantially smaller than the first depths;

forming a plurality of impurity accumulation regions at second portions of the drift regions adjacent to the source/drain regions by doping third impurities with third impurity concentrations into the second portions of the drift regions adjacent to the source/drain regions such that each of the plurality of impurity accumulation regions formed have a third impurity, a third impurity concentration and a third depth, and wherein the third depths of the impurity accumulation regions are substantially smaller than the first depths;

forming a gate insulation layer pattern on the semiconductor substrate, wherein the gate insulation layer pattern has openings that partially expose the source/drain regions;

forming a gate conductive layer pattern on a portion of the gate insulation layer pattern where the channel region is positioned; and

forming a buffer layer on the gate insulation layer pattern and the gate conductive layer pattern.

13. The method of claim 12, wherein the first, the second and the third impurities comprise substantially the same elements.

14. The method of claim 13, wherein first, the second and the third impurities comprise elements in Group III.

15. The method of claim 13, wherein first, the second and the third impurities comprise elements in Group V.

16. The method of claim 12, wherein the second impurity concentrations are substantially larger than the third impurity concentrations, and the third impurity concentrations are substantially larger than the first impurity concentrations.

17. The method of claim 12, wherein the second depths are substantially larger than the third depths.

18. The method of claim 12, wherein the source/drain regions are spaced apart from the channel region.

19. The method of claim 12, wherein the impurity accumulation regions are adjacent to the source/drain regions whereas the impurity accumulation regions are spaced apart from the channel region.

20. The method of claim 12, wherein the gate insulation layer pattern comprises silicon oxide or metal oxide layer, the gate conductive layer pattern comprises metal, metal nitride or polysilicon doped with impurities, and the buffer layer comprises silicon nitride or silicon oxynitride.

21. The method of claim 12, further comprising:

forming an isolation layer at an upper portion of the semiconductor substrate to define an active region and a field region; and

forming a deep well region in the semiconductor substrate to enclose the channel region and the drift regions by doping impurities different from the first impurities with an impurity concentration substantially smaller than the first impurity concentrations, wherein the deep well region has a fourth depth substantially larger than the first depths.

22. The method of claim 12, wherein forming the impurity accumulation regions are performed together with doping impurities for adjusting a threshold voltage into a portion of the semiconductor substrate adjacent to the high-voltage semiconductor device.

23. The method of claim 12, wherein forming the buffer layer is performed together with forming an etch stop layer or a silicidation preventing layer on a portion of the semiconductor substrate adjacent to the high-voltage semiconductor substrate.