Increasing breakdown voltage in semiconductor devices with vertical series capacitive structures
First Claim
1. A semiconductor device comprising:
- a) a top region, an intermediate region, a bottom region;
b) a controllable current path traversing any of said regions;
c) an insulating trench coextensive with and girding said top region and said intermediate region;
d) a series capacitive structure disposed in said insulating trench and having a biased top element;
wherein said intermediate region has a capacitive property for establishing a capacitive coupling between said series capacitive structure and said intermediate region, thereby maximizing the breakdown voltage in said current path.
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Abstract
This invention relates to an apparatus and method for achieving high breakdown voltage and low on-resistance in semiconductor devices that have top, intermediate and bottom regions with a controllable current path traversing any of these regions. The device has an insulating trench that is coextensive with the top and intermediate regions and girds these regions from at least one side and preferably from both or all sides. A series capacitive structure with a biased top element and a number of floating elements is disposed in the insulating trench, and the intermediate region is endowed with a capacitive property that is chosen to establish a capacitive interaction or coupling between the series capacitive structure and the intermediate region so that the breakdown voltage VBD is maximized and on-resistance is minimized. The capacitive property of the intermediate region is established by an appropriately chosen material constitution and is further controlled by a predetermined constitution of the insulating trench. The apparatus and method of invention are useful in any number of semiconductor devices including, among other, transistors, bipolar transistors, MOSFETs, JFETs, thyristors and diodes.
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Citations
38 Claims
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1. A semiconductor device comprising:
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a) a top region, an intermediate region, a bottom region;
b) a controllable current path traversing any of said regions;
c) an insulating trench coextensive with and girding said top region and said intermediate region;
d) a series capacitive structure disposed in said insulating trench and having a biased top element;
wherein said intermediate region has a capacitive property for establishing a capacitive coupling between said series capacitive structure and said intermediate region, thereby maximizing the breakdown voltage in said current path. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method for maximizing the breakdown voltage in a semiconductor device having a top region, an intermediate region and a bottom region and a controllable current path traversing any of said regions, said method comprising:
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a) providing an insulating trench coextensive with and girding said top region and said intermediate region;
b) disposing a series capacitive structure in said insulating trench;
c) biasing a top element of said series capacitive structure; and
d) adjusting a capacitive property of said intermediate region to establish a capacitive coupling between said series capacitive structure and said intermediate region to maximize the breakdown voltage in said current path. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33)
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34. A semiconductor device having cells, each of said cells comprising:
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a) a top region, an intermediate region and a bottom region;
b) a controllable current path traversing any of said regions;
c) an insulating trench coextensive with and girding said top region and said intermediate region;
d) a series capacitive structure disposed in said insulating trench and having a biased tip conductor;
said intermediate region having a capacitive property establishing a capacitive coupling between said series capacitive structure and said intermediate region, thereby maximizing the breakdown voltage in said current path. - View Dependent Claims (35, 36, 37, 38)
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Specification