Elimination of gate oxide weak spot in deep trench

• US 20060255402A1
• Filed: 05/12/2005
• Published: 11/16/2006
• Est. Priority Date: 05/12/2005
• Status: Active Grant

• Current Assignee: M-Mos Sdn., Bhd., M-Mos Semiconductor Sdn. Bhd.
• Original Assignee: M-Mos Sdn., Bhd.
• Inventors: Hshieh, Fwu-Iuan, Fai, Yee Ai, Keong, Ng Yeow
• Granted Patent: US 8,115,252 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A MOSFET with a 0.7˜2.0 micrometers deep trench is formed by first carrying out a processing step of opening a trench in a semiconductor substrate. A thick insulator layer is then deposited in the trench such that the film at the bottom of the trench is much thicker than the sidewall of the trench. The insulator layer at the sidewall is then removed followed by the creation of composite dual layers that form the Gate Oxide. Another embodiment has the insulator layer deposited after Gate Oxide growth and stop at a thin Nitride layer which serves as stop layer during insulator pullback at trench sidewall and during Polysilicon CMP. Embodiments of the present invention eliminates weak spot at trench bottom corner encountered when Gate Oxide is grown in a 0.2 micrometers deep trench with thick bottom oxide. The present invention also maintains good control of the shape of the trench and the thickness profile of the Gate Oxide

Claims

1. A electronic device supported on a semiconductor substrate comprising:

a trench opened in said semiconductor substrate wherein said trench further includes a thick dielectric layer disposed at a bottom of said trench; and

a composite dual dielectric layers covering a trench side wall and a trench bottom corner interfacing between said trench sidewall and said thick layer of insulation material.

2. The electronic device of claim 1 wherein:

said composite dual dielectric layers include a thermally grown inner oxide layer and a chemically deposited outer oxide layer.

3. The electronic device of claim 1 wherein:

said trench is approximately 0.7 to 2.0 micrometers deep.

4. The electronic device of claim 1 wherein:

said trench is less than 0.5 micrometers wide.

5. The electronic device of claim 1 wherein:

said trench is approximately 0.7 to 2.0 micrometers deep and said thick dielectric layer has a thickness approximately between 0.1 to 0.3 micrometers.

6. The electronic device of claim 1 wherein:

said composite dual insulation layers include a thermally grown inner oxide layer of approximately 200 to 1000 A in thickness and a chemically deposited outer oxide layer of approximately 200 to 600 A in thickness.

7. The electronic device of claim 1 wherein:

said composite dual dielectric layers include an oxide layer and a nitride outer oxide layer.

8. The electronic device of claim 1 wherein:

said composite dual dielectric layers include an oxide layer and an oxynitride outer oxide layer.

9. The electronic device of claim 1 wherein:

said thick dielectric layer disposed at said bottom of said trench further comprising a local oxidation of silicon (LOCOS) layer.

10. The electronic device of claim 1 wherein:

said thick dielectric layer disposed at said bottom of said trench further comprising a combination of local oxidation of silicon (LOCOS) and oxide layer.

11. The electronic device of claim 1 wherein:

said thick dielectric layer disposed at said bottom of said trench further comprising a combination of thermally grown oxide layer and deposit oxide layer.

12. The electronic device of claim 1 wherein:

said thick dielectric layer disposed at said bottom of said trench further comprising a combination of deposit oxide and nitride layer.

14. The MOSFET device of claim 1 wherein:

said composite dual dielectric layers include a thermally grown inner oxide layer and a chemically deposited outer oxide layer.

15. The MOSFET device of claim 1 wherein:

said trench is approximately 0.7 to 2.0 micrometers deep.

16. The MOSFET device of claim 1 wherein:

said trench is less than 0.5 micrometers wide.

17. The MOSFET device of claim 1 wherein:

said trench is approximately 0.7 to 2.0 micrometers deep and said thick dielectric layer has a thickness approximately between 0.1 to 0.3 micrometers.

18. The MOSFET device of claim 1 wherein:

said composite dual insulation layers include a thermally grown inner oxide layer of approximately 200 to 1000 A in thickness and a chemically deposited outer oxide layer of approximately 200 A to 600 A in thickness.

19. The MOSFET device of claim 1 wherein:

said composite dual dielectric layers include an oxide layer and a nitride outer oxide layer.

20. The MOSFET device of claim 1 wherein:

said composite dual dielectric layers include an oxide layer and an oxynitride outer oxide layer.

21. The MOSFET device of claim 1 wherein:

said thick dielectric layer disposed at said bottom of said trench further comprising a local oxidation of silicon (LOCOS) layer.

22. The MOSFET device of claim 1 wherein:

said thick dielectric layer disposed at said bottom of said trench further comprising a combination of local oxidation of silicon (LOCOS) and oxide layer.

23. The MOSFET device of claim 1 wherein:

said thick dielectric layer disposed at said bottom of said trench further comprising a combination of thermally grown oxide layer and deposit oxide layer.

24. The MOSFET device of claim 1 wherein:

said thick dielectric layer disposed at said bottom of said trench further comprising a combination of deposit oxide and nitride layer.

13. A MOSFET device supported on a semiconductor substrate comprising:

a trench opened in said semiconductor substrate wherein said trench further includes a thick dielectric layer disposed at a bottom of said trench; and

a composite dual dielectric layers covering a trench side wall and a trench bottom corner interfacing between said trench sidewall and said thick layer of insulation material.

25. A method for manufacturing an electronic device on a semiconductor substrate comprising:

opening a trench in said semiconductor substrate and depositing a thick dielectric layer at a bottom of said trench; and

forming a composite dual dielectric layers for covering a trench side wall and covering a trench bottom corner interfacing between said trench sidewall and said thick layer of insulation material.

26. The method of claim 25 wherein:

said step of forming said composite dual dielectric layers further comprising a step of thermally growing an inner oxide layer and chemically depositing an outer oxide layer.

27. The method of claim 25 wherein:

said step of opening said trench further comprising a step of opening said trench with approximately 0.7 to 2.0 micrometers in depth.

28. The method of claim 25 wherein:

said step of opening said trench further comprising a step of opening said trench with a width substantially narrower than 0.5 micrometers.

29. The method of claim 25 wherein:

said step of opening said trench further comprising a step of opening said trench with approximately 0.7 to 2.0 micrometers in depth; and

said step of depositing said thick dielectric layer further comprising a step of depositing said dielectric layer of approximately 0.1 to 0.3 micrometers in thickness.

30. The method of claim 25 wherein:

said step of forming said composite dual dielectric layers further comprising a step of thermally growing an inner oxide layer of approximately 0.02 to 0.10 micrometers in thickness and chemically depositing an outer oxide layer of approximately 200 Angstroms to 600 Angstroms in thickness.

31. The method of claim 25 wherein:

said step of forming said composite dual dielectric layers further comprising a step of thermally growing an inner oxide layer and chemically depositing an outer nitride layer.

32. The method of claim 25 wherein:

said step of forming said composite dual dielectric layers further comprising a step of thermally growing an inner oxide layer and chemically depositing an outer oxynitride layer.

33. The method of claim 25 wherein:

said step of depositing said thick dielectric layer further comprising a step of depositing a local oxidation of silicon layer at said bottom of said trench.

34. The method of claim 25 wherein:

said step of depositing said thick dielectric layer further comprising a step of depositing a combination of a local oxidation of silicon (LOCOS) layer and an oxide layer at said bottom of said trench.

35. The method of claim 25 wherein:

said step of depositing said thick dielectric layer further comprising a step of thermally grown an oxide layer and combining with depositing an oxide layer.

36. The method of claim 25 wherein:

said step of depositing said thick dielectric layer further comprising a step of depositing a combination of oxide and nitride layer.