Baseband signal processor

• US 20060255996A1
• Filed: 04/04/2006
• Published: 11/16/2006
• Est. Priority Date: 04/08/2005
• Status: Abandoned Application

• Current Assignee: Pine Valley Investments, Inc. (L3Harris Technologies, Inc.)
• Original Assignee: M/A-Com Incorporated and M/A-Com Eurotec BV
• Inventors: Li, Chin, Ahmed, Walid Khairy Mohamed, Carey, Eoin, Sheehy, Paul B., Quilligan, Gerard
• Application Number:
  US11/398,060
• Publication Number:
  US 20060255996A1
• Time in Patent Office: Days
• US Class Current: 341/156
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2203/45356 the AAC comprising one or more op-amps, e.g. IC-blocks
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03H 11/245 using field-effect transistor
• CPC Class Codes: H03M 1/0854 of quantisation noise
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H04W 52/52 using AGC [Automatic Gain Control] circuits or amplifiers

Abstract

A power control module receives a dynamic power control signal and generates a differential bias signal proportional to the dynamic power control signal. An analog multiplexer receives a digital amplitude signal including n bits and receives the differential bias signal. The analog multiplexer multiplexes the digital amplitude signal with the differential bias signal in parallel and generates a first differential signal. A driver module receives the first differential signal and a second differential signal. The driver module generates a first drive signal proportional to the dynamic power control signal when a bit in said digital amplitude signal is a logic one and the driver module generates a second drive signal proportional to the second differential signal when a bit in said digital amplitude signal is a logic zero.

Claims

1. A baseband processor, comprising:

a power control module to receive a dynamic power control signal and to generate a differential bias signal proportional to said dynamic power control signal;

an analog multiplexer to receive a digital amplitude signal comprising n bits and to receive said differential bias signal, said analog multiplexer to multiplex said digital amplitude signal with said differential bias signal in parallel to generate a first differential signal; and

a driver module to receive said first differential signal and to receive a second differential signal and to generate a first drive signal proportional to said dynamic power control signal when a bit in said digital amplitude signal is a logic one and to generate a second drive signal proportional to said second differential signal when a bit in said digital amplitude signal is a logic zero.

2. The baseband processor of claim 1, wherein said first differential signal is proportional to said dynamic power control signal.

3. The baseband processor of claim 1, wherein said power control module is to generate a common mode signal and wherein said differential bias signal is complementary and superimposed on said common mode signal.

4. The baseband processor of claim 1, further comprising an offset control module coupled to said driver module, said offset control module to receive said differential bias signal and to receive first and second offset signals, said offset control module to generate said second differential signal based on said differential bias signal and said first and second offset signals.

5. The baseband processor of claim 4, wherein said differential bias signal comprises first and second components, wherein said second differential signal comprises third and fourth components, and wherein said third component comprises said first component and said first offset signal and wherein said fourth component comprises said second component and said second offset signal.

6. The baseband processor of claim 4, further comprising a digital-to-analog converter to generate said first and second offset signals.

7. The baseband processor of claim 1, further comprising a bias control module coupled to said driver module, said bias control module to generate a bias control signal to bias said driver module, wherein said bias control signal is proportional to a transconductance property of said driver module, and wherein said drive signal is independent of variations of said transconductance property.

8. The baseband processor of claim 7, wherein said bias control module is to determine a value of current gain (β

) of a transistor in an amplifier, and wherein said bias control signal is proportional to the inverse of said β

, and wherein said drive signal is proportional to the inverse of said β

.

9. The baseband processor of claim 1, wherein said analog multiplexer and said driver module comprise a differential signal processing topology.

10. The baseband processor of claim 1, further comprising a filter coupled between said analog multiplexer and said driver module.

11. A polar modulation transmitter system, comprising:

an amplifier comprising at least a first and second transistor, said first and second transistors are formed on the same substrate and have similar current gains (β

); and

a baseband processor to dynamically bias a driver module coupled to said amplifier, said baseband processor comprising;

a power control module to receive a dynamic power control signal and to generate a differential bias signal proportional to said dynamic power control signal; and

an analog multiplexer to receive a digital amplitude signal comprising n bits and to receive said differential bias signal, said analog multiplexer to multiplex said digital amplitude signal with said differential bias signal in parallel to generate a first differential signal;

wherein said driver module is coupled to at said least first transistor, said driver module to receive said first differential signal and to receive a second differential signal and to generate a first drive signal to drive said at least first transistor, said drive signal proportional to said dynamic power control signal, when a bit in said digital amplitude signal is a logic one and to generate a second drive signal to drive said at least first transistor, said second drive signal proportional to said second differential signal, when a bit in said digital amplitude signal is a logic zero.

12. The system of claim 11, wherein said first differential signal is proportional to said dynamic power control signal.

13. The system of claim 11, further comprising an offset control module coupled to said driver module, said offset control module to receive said differential bias signal and to receive first and second offset signals, said offset control module to generate said second differential signal based on said differential bias signal and said first and second offset signals.

14. The system of claim 11, wherein said differential bias signal comprises first and second components, wherein said second differential signal comprises third and fourth components, and wherein said third component comprises said first component and said first offset signal and wherein said fourth component comprises said second component and said second offset signal.

15. The system of claim 11, further comprising a bias control module coupled to said driver module, said bias control module to generate a bias control signal to bias said driver module, wherein said bias control signal is proportional to a transconductance property of said driver module, and wherein said first and second drive signals are independent of variations of said transconductance property.

16. The system of claim 15, wherein said bias control module is to determine a value of current gain (β

) of said at least second transistor, and wherein said bias control signal is proportional to the inverse of said β

, and wherein said first and second drive signals are proportional to the inverse of said β

.

17. A method to dynamically bias a driver for power control and offset control, the method comprising:

receiving a dynamic power control signal;

generating a differential bias signal proportional to said dynamic power control signal;

receiving a digital amplitude signal;

multiplexing said differential bias signal with said digital amplitude signal in parallel; and

generating a first drive signal proportional to said dynamic power control signal when a bit in said digital amplitude signal is a logic one and generating a second drive signal proportional to said second differential signal when a bit in said digital amplitude signal is a logic zero.

18. The method of claim 17, comprising:

generating a common mode signal; and

superimposing said differential bias signal on said common mode signal.

19. The method of claim 17, comprising:

generating first and second offset signals; and

generating a second differential signal based on said differential bias signal and said first and second offset signals.

20. The method of claim 17, comprising:

generating a bias control signal proportional to a transconductance property of a driver module, wherein said first drive signal is independent of variations of said transconductance property; and

applying said bias control signal to said driver module.

21. The method of claim 20, comprising:

determining a value of current gain (β

) of a transistor in an amplifier; and

generating a bias control signal inversely proportional to said β

.

22. The method of claim 17, comprising:

filtering said first drive signal.