Integrated circuit package including miniature antenna

• US 20060256018A1
• Filed: 07/17/2006
• Published: 11/16/2006
• Est. Priority Date: 11/07/2002
• Status: Active Grant

• Current Assignee: Fractus SA
• Original Assignee: Fractus SA
• Inventors: Soler Castany, Jordi, Borja Borau, Carmen, Anguera Pros, Jaume, Puenta Baliarda, Carles
• Granted Patent: US 7,463,199 B2
• Time in Patent Office: Days
• US Class Current: 343/700.MS
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85203 Thermocompression bonding
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/165 Containers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01Q 1/22 : by structural association with other equipment or articles
• CPC Class Codes: H01Q 1/2283 : mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 1/36 : Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewithH01Q1/08, H01Q1/14 take precedence
• CPC Class Codes: H01Q 1/38 : formed by a conductive layer on an insulating support patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface H01Q15/142
• CPC Class Codes: H01Q 1/40 : Radiating elements coated with or embedded in protective material
• CPC Class Codes: H01Q 13/10 : Resonant slot antennas
• CPC Class Codes: H01Q 9/045 : with particular feeding means for circular polarisation H01Q9/0428
• CPC Class Codes: H01Q 9/26 : with folded element or elements, the folded parts being spaced apart a small fraction of operating wavelength resonant loop antennas H01Q7/00
• CPC Class Codes: H01Q 9/30 : with feed to end of elongated active element, e.g. unipole H01Q9/44 takes precedence
• CPC Class Codes: H01Q 9/40 : Element having extended radiating surface
• CPC Class Codes: H01Q 9/42 : with folded element, the folded parts being spaced apart a small fraction of the operating wavelength

Abstract

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna, each of the five sections or segments forming a pair of angles with each adjacent segment or section, wherein the smaller angle of each of the four pairs of angles between sections or segments is less than 180° (i.e., no pair of sections or segments define a longer straight segment), wherein at least two of the angles are less than 115°, wherein at least two of the angles are not equal, and wherein the curve fits inside a rectangular area the longest edge of which is shorter than one-fifth of the longest free-space operating wavelength of the antenna.

Claims

1. An integrated circuit package comprising:

at least one substrate, each substrate including at least one layer;

at least one semiconductor die located on at least one substrate;

at least one terminal;

an antenna located in said integrated circuit package but not on said at least one semiconductor die, said antenna comprising a conducting pattern, at least a portion of which includes a curve, wherein said curve comprises at least five segments, each of said at least five segments forming a pair of angles with each adjacent segment in said curve, at least three of said segments being shorter than one-tenth of the longest free-space operating wavelength of said antenna;

wherein the smaller angle of the pair of angles between adjacent segments is less than 180° and

at least two of said angles between adjacent segments are less than 115°

, wherein at least two of said angles are not equal; and

wherein said conducting pattern fits inside a rectangular area, the longest side of said rectangular area being shorter than one-fifth of the longest free-space operating wavelength of said antenna

2. An integrated circuit package as defined in claim 1, wherein two of said angles are defined respectively in the clockwise and counter-clockwise directions at opposite sides of the curve.

3. An integrated circuit package as defined in claim 1, wherein said at least two of said angles which are not equal are at least two of said smaller angles.

4. An integrated circuit package as defined in claim 1, wherein said at least two angles that are less than 115°

are defined in the clockwise and counter-clockwise directions at opposite sides of said curve.

5. An integrated circuit package as defined in claim 1, wherein said conducting pattern fits inside a rectangular area, the longest side of said rectangular area being shorter than one-twentieth of the longest free-space operating wavelength of said antenna.

6. An integrated circuit package as defined in claim 1, wherein at least one of said segments is non-linear and further wherein the shortest distance between any point on said curve having said at least one non-linear segment and a similarly-shaped curve formed entirely of linear segments is less than one-tenth of the longest free-space operating wavelength of said antenna.

7. An integrated circuit package as defined in claim 1, wherein said curve has a box-counting dimension larger than 1.17, said box-counting dimension being computed by means of a first and second rectangular grid, said grids fitting inside the smallest rectangular area enclosing said curve, said first grid comprises at least 5×

5 equal-sized cells and said second grid having a same size as said first grid, but with four times the number of cells, said cells of said second grid being scaled down by a factor of two with respect to the cells of said first grid.

8. An integrated circuit package as defined in claim 7, wherein the box-counting dimension of said curve is also larger than 1.2.

9. An integrated circuit package as defined in claim 7, wherein the box-counting dimension of said curve is also larger than 1.25.

10. An integrated circuit package as defined in claim 7, wherein the box-counting dimension of said curve is also larger than 1.3.

11. An integrated circuit package as defined in claim 7, wherein the box-counting dimension of said curve is also larger than 1.35.

12. An integrated circuit package as defined in claim 7, wherein the box-counting dimension of said curve is also larger than 1.4.

13. An integrated circuit package as defined in claim 7, wherein the box-counting dimension of said curve is also larger than 1.5.

14. An integrated circuit package as defined in claim 7, wherein the box-counting dimension of said curve is also larger than 1.7.

15. An integrated circuit package as defined in claim 1, wherein said curve has a box-counting dimension between ⅕

and 3, inclusive, said box-counting dimension being computed by means of a first and a second rectangular grid, said grids fitting inside the smallest rectangular area enclosing said curve, said first grid including at least 5×

5 equal-sized cells and said second grid having a same size as said first grid, but with four times the number of cells, said cells of said second grid being scaled down by a factor of two with respect to the cells of said first grid.

16. An integrated circuit package as defined in claim 1, wherein said curve has a box-counting dimension of about 2, said box-counting dimension being computed by means of a first and a second rectangular grid, said grids fitting inside the smallest rectangular area enclosing said curve, said first grid comprises at least 5×

5 equal-sized cells and said second grid having a same size as said first grid, but with four times the number of cells, said cells of said second grid being scaled down by a factor of two with respect to the cells of said first grid.

17. An integrated circuit package as defined in claim 1, wherein said curve has a box-counting dimension between 1.1 and 3, inclusive, said box-counting dimension being computed by means of a first and second rectangular grid, said grids fitting inside the smallest rectangular area enclosing said curve, said first grid comprises at least 10×

10 equal-sized cells and said second grid having the same size as said first grid, but with four times the number of cells of said second grid being scaled down by a factor of two with respect to the cells of said first grid.

18. An integrated circuit package as defined in claim 7, wherein said curve crosses at least 14 of the 25 equal cells of said first grid.

19. An integrated circuit package as defined in claim 7, wherein said curve crosses at least 14 of the 25 equal cells of said first grid at least twice.

20. An integrated circuit package as defined in claim 1, wherein at least a portion of said curve is a space-filling curve

21. An integrated circuit package as defined in claim 20, wherein said space-filling curve is a Hilbert curve or a Peano curve.

22. An integrated circuit package as defined in claim 13, wherein said space-filling curve comprises at least one of SZ, ZZ HilbertAA, Peanoinc, Peanodec, and PeanoZZ.

23. An integrated circuit package as defined in claim 1, wherein said curve is formed on a single plane in said integrated circuit package and wherein said curve does not intersect itself at any point.

24. An integrated circuit package as defined in claim 1, wherein at least two of said segments of said curve are located on different layers within said integrated circuit package, said segments being connected by one or more vias.

25. An integrated circuit package as defined in claim 24, wherein said two segments located on different layers are located on opposite sides of a two-sided layer within said integrated circuit package.

26. An integrated circuit package as defined in claim 17, wherein said two segments located on different layers are located on two different substrates within said integrated circuit package.

27. An integrated circuit package as defined in claim 1, wherein said package includes at least a second conducting pattern having two ends, one of said two ends being connected to a point of said conducting pattern, said conducting pattern and said second conducting pattern fitting together inside a rectangular area, the longest side of said rectangular area being shorter than one-fifth of the longest free-space operating wavelength of said antenna.

28. An integrated circuit package as defined in claim 1, wherein said curve is the radiating arm of a monopole antenna, said radiating arm including at least one feeding point connected to said at least one semiconductor die either directly, or indirectly by means of at least one of a passive or active RF network, said integrated circuit package further including:

at least one ground terminal to connect the integrated circuit package; and

at least one RF connection of said semiconductor die to at least one of a ground plane or a ground counterpoise.

29. An integrated circuit package as defined in claim 28, wherein said monopole antenna is a folded monopole antenna.

30. An integrated circuit package as defined in claim 1, wherein said curve defines at least a portion of at least one of the two radiating arms of a dipole antenna, said two arms including at least one feeding point on each arm, wherein said at least two feeding points are connected to said at least one semiconductor die either directly, or indirectly by means of at least a passive or an active RF network.

31. An integrated circuit package as defined in claim 23, wherein said dipole antenna is a folded dipole antenna.

32. An integrated circuit package as defined in claim 1, wherein said curve is a slot in a conducting pattern, said pattern covering at least 50% of at least one of said layers of at least one of said substrates within said integrated circuit package.

33. An integrated circuit package as defined in claim 32, wherein said slot includes two feeding points, said points defining a differential input/output terminal, each of said two feeding points placed at opposite sides of said slot, said feeding points being fed by two conductors, said two conductors being at least one of wire bonds or conducting strips formed on the layer of the substrate containing said slot.

34. An integrated circuit package as defined in claim 33, wherein said slot is fed by a conducting strip, said conducting strip being located on a substrate layer above the layer on which the slot is located, said conducting strip crossing over the slot at at least one point.

35. An integrated circuit package as defined in claim 33, wherein said slot is fed by a conducting strip, said conducting strip being located on a substrate layer below the layer on which the slot is located, said conducting strip crossing below the slot at at least one point.

36. An integrated circuit package as defined in claim 33, wherein said slot is surrounded by the conducting material of said conducting pattern.

37. An integrated circuit package as defined in claim 33, wherein said slot intersects the perimeter of said conducting pattern at at least one point of said perimeter.

38. An integrated circuit package as defined in claim 33, wherein said conducting pattern is connected to at least one terminal of said integrated circuit package, said at least one terminal being adapted for connection to at least one of an external ground plane or a ground counterpoise.

39. An integrated circuit package as defined in claim 1, wherein said curve is at least a portion of the radiating arm of an inverted F antenna, said radiating arm including at least one feeding point on said curve, said at least one feeding point being connected to said at least one semiconductor die either directly, or indirectly by means of at least one of a passive or active RF network, said radiating arm connected to a first ground terminal of said integrated circuit package, said first ground terminal adapted for connection to at least one of an external ground plane or ground counterpoise, said integrated circuit package further including a second ground terminal adapted for connecting said at least one semiconductor die to at least one of an external ground plane or ground counterpoise.

40. An integrated circuit package as defined in claim 1, wherein said antenna comprises at least two radiating arms coupled together in a region wherein the distance between said at least two radiating arms is shorter than one-tenth of the longest free-space operating wavelength of said antenna.

41. An integrated circuit package as defined in claim 40, wherein said arms comprise the two radiating arms of a dipole antenna.

42. An integrated circuit package as defined in claim 40, wherein said curve comprises first and second radiating arms, said first radiating arm includes at least one feeding point, said at least one feeding point being connected to said at least one semiconductor die either directly, or indirectly by means of at least one of a passive or an active RF network, said integrated circuit package including:

at least one grounding terminal to connect the package to at least one of a ground plane or ground counterpoise, said at least one semiconductor die is connected to a first grounding terminal of said integrated circuit package; and

said second radiating arm is a parasitic element having no feeding point, but having a grounding point that is connected to a second grounding terminal in said integrated circuit package; and

wherein said first and second grounding terminals are adapted for connection to at least one of an external ground plane or ground counterpoise.

43. An integrated circuit package as defined in claim 1, wherein said curve is at least a portion of a closed curve, said closed curve defining a loop antenna, or a slot-loop antenna.

44. An integrated circuit package as defined in claim 1, wherein said conducting pattern defines at least a portion of the perimeter of the radiating surface of at least one of a microstrip, patch or planar inverted F antenna, said curve comprising at least fifteen segments;

wherein at least seven of said segments are shorter than one-twentieth of the longest free-space operating wavelength of said antenna;

wherein said conducting pattern includes at least one feeding point, said at least one feeding point being connected to said at least one semiconductor die by means either directly, or indirectly by means of at least one of a passive or an active RF network; and

wherein said integrated circuit package is mounted over an external ground plane or ground counterpoise so that said ground plane or ground counterpoise completely covers the area underneath said integrated circuit package.

45. An integrated circuit package as defined in claim 44, wherein said conducting pattern is formed on a first substrate layer in said integrated circuit package, said integrated circuit package including a second conducting pattern located on a second substrate layer in said integrated circuit package, said second conducting pattern acting as the ground plane for said at least one of a microstrip, a patch or a planar inverted F antenna.

46. An integrated circuit package as defined in claim 1, wherein the connections between said at least one semiconductor die and said at least one terminal of said integrated circuit package are a plurality of conducting strips.

47. An integrated circuit package as defined in claim 1, wherein said curve is located on the top surface of said at least one substrate, and further wherein said at least one semiconductor die is mounted on the same substrate surface as said curve.

48. An integrated circuit package as defined in claim 1, wherein said integrated circuit package includes at least one substrate having a plurality of layers, and further wherein said curve is located on at least two of said layers.

49. An integrated circuit package as defined in claim 1, wherein said curve is located on at least one of said layers of said substrates and further wherein said integrated circuit package includes at least one additional conducting pattern, said additional conducting pattern modifies a property of said antenna, the antenna property being selected from the group consisting of the impedance and impedance bandwidth, the antenna resonant frequency, the antenna radiation pattern, and combinations thereof.

50. An integrated circuit package as defined in claim 1, wherein said integrated circuit package includes at least two substrates;

wherein said curve is located on a top surface of one of said substrates; and

wherein said at lest one semiconductor die is mounted on a different substrate surface from said curve; and

wherein said curve and said at least one semiconductor die are located on parallel surfaces.

51. An integrated circuit package as defined in claim 1, wherein the integrated circuit package does not include any metallization above or below the antenna conducting pattern, except for wires or strips used to connect the at least one semiconductor die with the terminals of said integrated circuit package.

52. An integrated circuit package as defined in claim 1, wherein the integrated circuit package includes at least one additional metallization located on a substrate layer parallel to the substrate layer on which the curve is located, wherein the area containing said additional metallization covers less than 50% of the rectangular area enclosing said curve.

53. An integrated circuit package as defined in claim 32, wherein said slot antenna is located on a first substrate in said integrated circuit package;

wherein said at least one semiconductor die is located on a second substrate in said integrated circuit package, said two substrates being connected by at least one via or post; and

wherein the minimum area containing said slot antenna covers at least 80% of the total footprint of said integrated circuit package.

54. An integrated circuit package as defined in claim 53, wherein said at least one semiconductor die is a flip-chip, said flip-chip including a shielding conducting layer at the opposite face of the terminals, and wherein said slot antenna is positioned over said flip-chip so that said flip-chip-is located between said first and second substrates.

55. An integrated circuit package as defined in claim 1, wherein the connections between said at least one semiconductor die and the terminals of said integrated circuit package are located on a first layer of a substrate in said integrated circuit package;

wherein said curve is located on the same substrate as said connections but on a different layer of said substrate that is substantially parallel to a first layer of said substrate where said connections are located.

56. An integrated circuit package as defined in claim 1, wherein each time a conducting strip on a first layer crosses above or below said curve on a second layer, the conducting strip and the curve lie in a direction perpendicular to one another.

57. An integrated circuit package as defined in claim 1, wherein said integrated circuit package includes:

a two-dimensional array of at least one of pins or solder balls on a first layer of at least one substrate in said integrated circuit package and wherein said curve is located on a different layer above said first layer, said two-dimensional array of at least one of pins or solder balls fits inside a rectangular grid having the same number of cells as there are at least one of pins or solder balls in the two-dimensional array, each pin or solder ball is located in the center of a cell of the rectangular grid so that the grid is equidistant from each of said pins or solder balls; and

wherein all of said angles between adjacent segments of said curve are 90°

so that said curve follows a path along said rectangular grid between said pins or solder balls.

58. An integrated circuit package as defined in claim 1, wherein terminals are pin connections which surround the perimeter of the package and are connected to the chip directly by means of at least one of wire bonds or by conducting strips on top of the package substrate, and further wherein a metal frame includes both terminals and conducting strips that are connected through wire bonds to the chip.

59. An integrated circuit package as defined in claim 1, wherein said curve is repeated in two or more layers within at least one of the substrates of said integrated circuit package, and wherein all of said curves are connected through at least one via at the feeding points of said curves.

60. An integrated circuit package as defined in claim 1, wherein said at least one semiconductor die and said curve are connected through capacitive coupling, said coupling being provided by two conducting elements separated by a dielectric material, each of said conducting elements being connected ohmically to said curve and said at least one semiconductor die, respectively.

61. An integrated circuit package as defined in claim 1, wherein said conducting pattern is a first conducting pattern located on a first layer of at least one of said substrates in said integrated circuit package, said first conducting pattern being coupled or connected to said at least one semiconductor die, said integrated circuit package further including:

at least a second conducting pattern located on a second layer of said substrate, said second curve being at least one of capacitively or inductively coupled to said first conducting pattern, said second conducting pattern acting as a parasitic element for said first curve.

62. An integrated circuit package as defined in claim 1, wherein said curve is adapted for electromagnetic coupling to an external antenna, said external antenna acting as a parasitic antenna for said curve.

63. An integrated circuit package as defined in claim 1, wherein said integrated circuit package is constructed by a technique selected from the group consisting of MCM-L, MCM-C, MCM-D and MCM-D/L.

64. An integrated circuit package as defined in claim 1, wherein said integrated circuit package is selected from the group consisting of single-in-line, dual-in-line, DIL-SMT, quad-flat-package, pin grid array, ball grid array, PBGA, CBGA, TBGA, SBGA, and BGA.

65. An integrated circuit package as defined in claim 1, wherein said integrated circuit package is encapsulated in plastic, said curve located on said plastic encapsulating said integrated circuit package and capacitively coupled to a second curve located in said integrated circuit package, or to said at least one semiconductor die.

66. An integrated circuit package as defined in claim 65, wherein said curve is formed on said plastic encapsulating said integrated circuit package by a technique selected from the group consisting of a two-shot injection process, a co-injection process, an insert molding process and an MID process.

67. An integrated circuit package as defined in claim 1, wherein said integrated circuit package is smaller than 10 mm by 10 mm, and said antenna is resonant at a frequency between 0.5 and 5.5 GHz.

68. An integrated circuit package as defined in claim 1, wherein said integrated circuit package is smaller than 100 square millimeters, and said antenna is resonant at a frequency between 0.5 and 5.5 GHz.

69. An integrated circuit package as defined in claim 1, wherein said integrated circuit package is smaller than 16 square millimeters, and said antenna is resonant at a frequency of 2.4 GHz.

71. An integrated circuit package as defined in claim 1, wherein said integrated circuit package contains or is integrated in a sensor for measuring at least one parameter selected from the group consisting of temperature, pressure, tension, traction, acceleration, vibration, distance, speed, rotation, light intensity, electromagnetic field intensity, chemical concentration of a chemical component inside a material, electromagnetic or acoustic Doppler shift or motion.

An integrated circuit package comprising:

at least one substrate, each substrate including at least one layer;

at least one semiconductor die located on at least one substrate;

an antenna located in said integrated circuit package but not on said at least one semiconductor die, said antenna comprising a conducting pattern, at least a portion of which includes a curve, wherein said curve comprises at least five segments, each of said at least five segments forming a pair of angles with each adjacent segment in said curve, at least three of said segments being shorter than one-tenth of the longest free-space operating wavelength of said antenna;

wherein the smaller angle of the pair of angles between adjacent segments is less than 180° and

at least two of said angles between adjacent segments are less than 115°

, wherein at least two of said angles are not equal; and

wherein said conducting pattern fits inside a rectangular area, the longest side of said rectangular area being shorter than one-fifth of the longest free-space operating wavelength of said antenna;

at least one terminal connected to at least one of said semiconductor die and said antenna

70. An integrated circuit package as defined in claim 1, wherein said antenna operates for at least one system selected from the group consisting of Bluetooth™

, IEEE802.11a, IEEE802.11b, Hyperlan, Hyperlan2, UMTS, GSM900, DCS, GSM1800, PCS1900, CDMA-800, PDC-800, PDC-1500, KPCS, AMPS, WCDMA, DECT, UWB and GPS.

70-1. An integrated circuit package comprising:

at least one substrate, each substrate including at least one layer;

at least one semiconductor die located on at least one substrate;

an antenna located in said integrated circuit package but not on said at least one semiconductor die, said antenna comprising a conducting pattern, at least a portion of which includes a curve, wherein said curve comprises at least five segments, each of said at least five segments forming a pair of angles with each adjacent segment in said curve, at least three of said segments being shorter than one-tenth of the longest free-space operating wavelength of said antenna;

wherein the smaller angle of the pair of angles between adjacent segments is less than 180° and

at least two of said angles between adjacent segments are less than 115°

, wherein at least two of said angles are not equal; and

wherein said conducting pattern fits inside a rectangular area, the longest side of said rectangular area being shorter than one-fifth of the longest free-space operating wavelength of said antenna; and

at least one terminal connected to at least one of said semiconductor die and said antenna.