Enhanced programming performance in a nonvolatile memory device having a bipolar programmable storage element
First Claim
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1. A nonvolatile memory cell for use in a memory circuit, the memory cell comprising:
- a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element being adapted for connection to a first bit line in the memory circuit; and
a metal-oxide-semiconductor device including first and second source/drains and a gate, the first source/drain being connected to a second terminal of the bipolar programmable storage element, the second source/drain being adapted for connection to a second bit line in the memory circuit, and the gate being adapted for connection to a word line in the memory circuit.
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Abstract
A nonvolatile memory cell includes a bipolar programmable storage element operative to store a logic state of the memory cell, and a metal-oxide-semiconductor device including first and second source/drains and a gate. A first terminal of the bipolar programmable storage element is adapted for connection to a first bit line. The first source/drain is connected to a second terminal of the bipolar programmable storage element, the second source/drain is adapted for connection to a second bit line, and the gate is adapted for connection to a word line.
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Citations
20 Claims
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1. A nonvolatile memory cell for use in a memory circuit, the memory cell comprising:
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a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element being adapted for connection to a first bit line in the memory circuit; and
a metal-oxide-semiconductor device including first and second source/drains and a gate, the first source/drain being connected to a second terminal of the bipolar programmable storage element, the second source/drain being adapted for connection to a second bit line in the memory circuit, and the gate being adapted for connection to a word line in the memory circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A nonvolatile memory array, comprising:
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a plurality of bit lines and word lines; and
a plurality of nonvolatile memory cells operatively coupled to the bit lines and word lines for selectively accessing one or more memory cells in the memory array, at least one of the memory cells comprising;
a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to a corresponding first one of the bit lines; and
a metal-oxide-semiconductor device including first and second source/drains and a gate, the first source/drain being connected to a second terminal of the bipolar programmable storage element, the second source/drain connecting to a corresponding second one of the bit lines, and the gate connecting to a corresponding one of the word lines. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. An integrated circuit including at least one nonvolatile memory array, the at least one memory array comprising:
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a plurality of bit lines and word lines; and
a plurality of nonvolatile memory cells operatively coupled to the bit lines and word lines for selectively accessing one or more memory cells in the memory array, at least one of the memory cells comprising;
a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to a corresponding first one of the bit lines; and
a metal-oxide-semiconductor device including first and second source/drains and a gate, the first source/drain being connected to a second terminal of the bipolar programmable storage element, the second source/drain connecting to a corresponding second one of the bit lines, and the gate connecting to a corresponding one of the word lines.
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Specification