Enhanced programming performance in a nonvolatile memory device having a bipolar programmable storage element

• US 20060256611A1
• Filed: 08/31/2005
• Published: 11/16/2006
• Est. Priority Date: 05/13/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Meijer, Gerhard Ingmar, Sun, Jonathan Zanhong, Lam, Chung Hon, Bednorz, Johannes Georg, DeBrosse, John Kenneth
• Granted Patent: US 7,376,006 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A nonvolatile memory cell includes a bipolar programmable storage element operative to store a logic state of the memory cell, and a metal-oxide-semiconductor device including first and second source/drains and a gate. A first terminal of the bipolar programmable storage element is adapted for connection to a first bit line. The first source/drain is connected to a second terminal of the bipolar programmable storage element, the second source/drain is adapted for connection to a second bit line, and the gate is adapted for connection to a word line.

Claims

1. A nonvolatile memory cell for use in a memory circuit, the memory cell comprising:

a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element being adapted for connection to a first bit line in the memory circuit; and

a metal-oxide-semiconductor device including first and second source/drains and a gate, the first source/drain being connected to a second terminal of the bipolar programmable storage element, the second source/drain being adapted for connection to a second bit line in the memory circuit, and the gate being adapted for connection to a word line in the memory circuit.

2. The memory cell of claim 1, wherein the bipolar programmable storage element comprises a magnetic tunnel junction device.

3. The memory cell of claim 1, wherein the bipolar programmable storage element comprises a transition-metal oxide.

4. The memory cell of claim 1, wherein the metal-oxide-semiconductor device comprises a field effect transistor.

5. The memory cell of claim 1, wherein a logic state of the bipolar programmable storage element is written by substantially concurrently applying a logic high voltage potential to the word line, applying a logic high voltage potential to one of the first and second bit lines, and applying a logic low voltage potential to another of the first and second bit lines, a polarity of the voltage potential across the first and second bit lines being indicative of the logic state to be written into the memory cell.

6. The memory cell of claim 5, wherein the logic high voltage potential is about one volt and the logic low voltage potential is about zero volt.

7. The memory cell of claim 1, wherein a logic state of the bipolar programmable storage element is read by substantially concurrently applying a logic high voltage potential to the word line, applying a logic low voltage potential to one of the first and second bit lines, applying a read voltage potential to and sensing a current on another of the first and second bit lines, a magnitude of the sensed current being indicative of the logic state of the memory cell.

8. The memory cell of claim 7, wherein the logic high voltage potential is equal to about one volt and the logic low voltage potential is equal to about zero volt.

9. The memory cell of claim 1, wherein the bipolar programmable storage element is formed substantially directly above the metal-oxide-semiconductor device, so as to minimize a footprint of the memory cell.

10. The memory cell of claim 1, wherein a resistance state of the bipolar programmable storage element is programmed by applying one or more electrical pulses across the first and second terminals of the storage element, the electrical pulses having a voltage potential which is greater than a threshold voltage, Vt, of the storage element and a duration which is greater than a time, t.

11. The memory cell of claim 1, wherein a resistance state of the bipolar programmable storage element is read in a non-destructive manner by applying one or more electrical pulses across the first and second terminals of the storage element and measuring a current through the storage element, the electrical pulses having a voltage potential which is less than a threshold voltage, Vt, of the storage element and a duration which is less than a time, t.

12. A nonvolatile memory array, comprising:

a plurality of bit lines and word lines; and

a plurality of nonvolatile memory cells operatively coupled to the bit lines and word lines for selectively accessing one or more memory cells in the memory array, at least one of the memory cells comprising;

a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to a corresponding first one of the bit lines; and

a metal-oxide-semiconductor device including first and second source/drains and a gate, the first source/drain being connected to a second terminal of the bipolar programmable storage element, the second source/drain connecting to a corresponding second one of the bit lines, and the gate connecting to a corresponding one of the word lines.

13. The memory array of claim 12, wherein at least a subset of the memory cells are arranged such that a first one of the bit lines is connected to the first terminals of the bipolar programmable storage elements in a first and second one of the memory cells and connected to the second source/drains of the metal-oxide-semiconductor devices in a third and fourth one of the memory cells, and a second one of the bit lines is connected to the first terminals of the bipolar programmable storage elements in the third and fourth one of the memory cells, and the second source/drains of the metal-oxide-semiconductor devices in the first and second one of the memory cells, and wherein the gates of the first, second third and fourth one of the memory cells are connected to different word lines in the memory array.

14. The memory array of claim 12, wherein the plurality of bit lines are arranged substantially parallel relative to one another.

15. The memory array of claim 12, wherein the plurality of word lines are arranged substantially parallel relative to one another.

16. The memory array of claim 12, wherein the bipolar programmable storage element comprises a magnetic tunnel junction device.

17. The memory array of claim 12, wherein the bipolar programmable storage element comprises a transition-metal oxide.

18. The memory array of claim 12, wherein a logic state of the bipolar programmable storage element is written by substantially concurrently applying a logic high voltage potential to the word line, applying a logic high voltage potential to one of the first and second bit lines, and applying a logic low voltage potential to another of the first and second bit lines, a polarity of the voltage potential across the first and second bit lines being indicative of the logic state to be written into the memory cell.

19. The memory array of claim 12, wherein a logic state of the bipolar programmable storage element is read by substantially concurrently applying a logic high voltage potential to the word line, applying a logic low voltage potential to one of the first and second bit lines, applying a read voltage potential to and sensing a current on another of the first and second bit lines, a magnitude of the sensed current being indicative of the logic state of the memory cell.

20. An integrated circuit including at least one nonvolatile memory array, the at least one memory array comprising:

a plurality of bit lines and word lines; and

a plurality of nonvolatile memory cells operatively coupled to the bit lines and word lines for selectively accessing one or more memory cells in the memory array, at least one of the memory cells comprising;

a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to a corresponding first one of the bit lines; and

a metal-oxide-semiconductor device including first and second source/drains and a gate, the first source/drain being connected to a second terminal of the bipolar programmable storage element, the second source/drain connecting to a corresponding second one of the bit lines, and the gate connecting to a corresponding one of the word lines.