Flash memory array using adjacent bit line as source

• US 20060256618A1
• Filed: 05/12/2005
• Published: 11/16/2006
• Est. Priority Date: 05/12/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nazarian, Hagop A.
• Granted Patent: US 7,203,092 B2
• Time in Patent Office: Days
• US Class Current: 365/185.170
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays

Abstract

A memory array having a plurality of flash memory cells arranged in rows and columns. A plurality of bit lines couple the columns such that alternate bit lines of the plurality of bit lines are adapted to operate as either source lines or bit lines in response to bit line selection and biasing.

Claims

1. A memory array comprising:

a plurality of flash memory cells arranged in rows and columns; and

a plurality of bit lines coupling the columns such that alternate bit lines of the plurality of bit lines are adapted to operate as either source lines or bit lines in response to bit line selection.

2. The memory array of claim 1 wherein the alternate bit lines operate as source lines during predetermined memory operations.

3. The memory array of claim 2 wherein the predetermined memory operations comprise a memory read operation.

4. The memory array of claim 1 wherein each column of flash memory cells is arranged in a plurality of series strings of flash memory cells, each series string having a top select transistor and a bottom select transistor.

5. The memory array of claim 4 wherein the top select transistor is coupled to a first bit line and the bottom select transistor is coupled to a bit line that is adjacent to the first.

6. The memory array of claim 4 wherein select lines are coupled to control gates of alternate bottom select transistors.

7. The memory array of claim 4 wherein two adjacent top select transistors are coupled to a first bit line.

8. A NAND flash memory array comprising:

a plurality of flash memory cells arranged in rows and columns, each column of memory cells comprising a plurality of subsets of series coupled flash memory cells, each subset having a top select transistor and a bottom select transistor;

a plurality of word lines coupling the rows; and

a plurality of bit lines coupling the columns such that the top select transistor of each subset is coupled to a different bit line than the bottom select transistor.

9. The memory array of claim 8 wherein the different bit line is an adjacent bit line.

10. The memory array of claim 8 wherein control gates of the top select transistors and the bottom select transistors of each column are coupled together into rows.

11. The memory array of claim 8 wherein a control gate of a bottom select transistor is coupled to a control gate of an adjacent top select transistor in each column.

12. The memory array of claim 8 wherein a bottom select transistor of a first subset of series coupled flash memory cells in a first column is coupled to a top select transistor of a second subset of series coupled flash memory cells in the first column.

13. The memory array of claim 8 wherein subset is comprised of 32 flash memory cells connected in a series configuration between the top and the bottom select transistors.

14. A flash memory device comprising:

memory control circuit that controls operations of the memory device; and

a flash memory array comprising;

a plurality of flash memory cells arranged in rows and columns; and

a plurality of bit lines coupling the columns such that alternate bit lines of the plurality of bit lines are adapted to operate as either source lines or bit lines in response to bit line selection.

15. The device of claim 14 wherein unselected bit lines that are biased at ground potential operate as source lines.

16. The device of claim 14 wherein the columns are comprised of a plurality of subsets of series coupled flash memory cells, each subset having a top select transistor and a bottom select transistor such that adjacent column select transistors at the top and bottom of each column are coupled in rows.

17. The device of claim 14 wherein the columns are comprised of a plurality of subsets of series coupled flash memory cells, each subset having a top select transistor and a bottom select transistor such that a first bottom select transistor of a first subset is coupled serially at a common node to a first top select transistor of an adjacent subset and a control gate of the first bottom select transistor is coupled to a control gate of the first top select transistor.

18. The device of claim 17 wherein a select line couples rows of control gates of serially coupled select transistors in alternate columns.

19. The device of claim 17 wherein common nodes between serially coupled select transistors of a column are coupled in an alternate fashion to one of a first bit line or an adjacent bit line.

20. The device of claim 17 wherein a first common node of a first and a second adjacent column are coupled to a first bit line and a second common node of the first and second adjacent column are coupled to a second bit line that is adjacent to the first bit line.

21. An electronic system comprising:

a processor that generates memory control signals; and

a memory device comprising;

a memory array having a plurality of flash memory cells arranged in rows and columns; and

a plurality of bit lines coupling the columns such that alternate bit lines of the plurality of bit lines are adapted to operate as either source lines or bit lines in response to bit line selection.

22. A method for programming a memory array that includes a plurality of bit lines coupling series strings of memory cells such that alternate bit lines act as source lines, the method comprising:

biasing selected bit lines with a select voltage;

biasing unselected bit line with an inhibit voltage;

biasing selected word lines with at least one programming voltage; and

biasing a select gate drain line at a first voltage at a first time and a second voltage at a second time.

23. The method of claim 22 and further including biasing remaining select gate drain lines and select gate source lines at ground potential.

24. The method of claim 22 wherein biasing the selected word lines includes applying a series of programming pulses that start at a first programming voltage and increase at a predetermined incremental voltage.

25. The method of claim 22 wherein the select voltage is 0V and the inhibit voltage is V_CC.

26. The method of claim 24 wherein the incremental voltage is 0.5V.

27. The method of claim 24 and further including performing a verify operation between each programming pulse.

28. A method for reading a memory array that includes a plurality of bit lines coupling series strings of memory cells such that alternate bit lines act as source lines, the method comprising:

pre-charging selected bit lines to a pre-charge voltage;

biasing a select gate source line and a select gate drain line;

biasing the alternate bit lines at a predetermined voltage such that they act as source lines;

sensing the selected bit lines; and

releasing the bit lines that act as source lines.

29. The method of claim 28 and further including precharging an output of a sense amplifier.

30. The method of claim 28 wherein the predetermined voltage is 0V.

31. The method of claim 28 wherein the pre-charge voltage is 2V.

32. The method of claim 28 wherein the select gate drain line is biased at 4.5V and the select gate source line is biased at 1V.