Programming memory devices

• US 20060256620A1
• Filed: 05/11/2005
• Published: 11/16/2006
• Est. Priority Date: 05/11/2005
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Louie, Benjamin, Yip, Aaron, Han, Jin-Man, Nguyen, Dzung H., Nazarian, Hagop A.
• Granted Patent: US 7,269,066 B2
• Time in Patent Office: Days
• US Class Current: 365/185.280
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Claims

1. A method of programming a target memory cell of a memory device, comprising:

applying a programming voltage to a word line that includes the target memory cell;

determining whether the target memory cell is programmed; and

increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed;

wherein an initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

2. The method of claim 1, wherein the initial programming voltage is selected from a plurality of initial programming voltages.

3. The method of claim 1, wherein the step voltage is selected from a plurality of step voltages.

4. The method of claim 1 further comprises applying a pass voltage to word lines that do not include the target memory cell while applying the programming voltage to the word line that includes the target memory cell, wherein the pass voltage is insufficient for programming memory cells and activates memory cells of the word lines that do not include the target memory cell.

5. The method of claim 4, wherein the pass voltage is selectable after fabrication of the memory device.

6. The method of claim 5, wherein the pass voltage is selected from a plurality of pass voltages.

7. The method of claim 4 further comprises setting a length of a time allowed for a voltage applied to word lines that do not include the target memory cell and a voltage applied to the word line that includes the target memory cell to increase from an initial level to the pass voltage.

8. The method of claim 7, wherein the length of a time is selectable after fabrication of the memory device.

9. The method of claim 8, wherein setting the length of the time comprises selecting the length of time from a plurality of lengths of time.

10. The method of claim 1 further comprises applying a voltage to a source line selectively coupled to a NAND string of memory cells that includes the target memory cell by a source select gate.

11. The method of claim 10, wherein applying a voltage to the source line comprises applying Vcc to the source line.

12. The method of claim 1 further comprises applying a voltage to a drain select line coupled to a control gate of a drain select gate that selectively couples a bit line to a NAND string of memory cells that includes the target memory cell.

13. The method of claim 12, wherein applying the voltage to the drain select line comprises increasing the voltage to the drain select line from a first voltage level to a second voltage level and decreasing the voltage to the drain select line from the second level to a third voltage level, wherein the third voltage level is applied to the drain select line while applying the programming voltage to the word line that includes the target memory cell.

14. The method of claim 13, wherein the third voltage level is selectable after fabrication of the memory device.

15. The method of claim 14, wherein the third voltage level is selected from a plurality of third voltage levels.

16. The method of claim 13, wherein the second voltage level is Vcc.

17. The method of claim 16, wherein the third voltage is between Vss and Vcc.

18. The method of claim 1 further comprises applying a voltage to a source select line coupled to a control gate of a source select gate that selectively couples a source line to a NAND string of memory cells that includes the target memory cell.

19. The method of claim 18, wherein applying the voltage to the source select line comprises applying Vss to the source select line.

20. The method of claim 1 further comprises applying a voltage to a bit line selectively coupled to a NAND string of memory cells that includes the target memory cell.

21. The method of claim 20, wherein applying the voltage to the bit line comprises applying an inhibit voltage to the bit line to prevent programming of the target memory cell.

22. The method of claim 1 further comprises setting a length of a time that the programming voltage is applied to the word line that includes the target memory cell.

23. The method of claim 22, wherein the length of a time is selectable after fabrication of the memory device.

24. The method of claim 23, wherein setting the length of the time comprises selecting the length of time from a plurality of lengths of time.

25. A method of programming a target memory cell of a memory device, comprising:

applying a programming voltage to a word line that includes the target memory cell;

applying a pass voltage to word lines that do not include the target memory cell while applying the programming voltage to the word line that includes the target memory cell for turning on memory cells of the word lines that do not include the target memory cell;

applying a voltage to a bit line selectively coupled to a NAND string of memory cells that includes the selected memory cell;

determining whether the target memory cell is programmed; and

increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed;

wherein an initial programming voltage, the step voltage, and the pass voltage are each selectable after fabrication of the memory device.

26. The method of claim 25, wherein the initial programming voltage, the step voltage, and the pass voltage are respectively selected from a plurality of initial programming voltages, a plurality of step voltages, and a plurality of pass voltages.

27. The method of claim 25, wherein applying the voltage to the bit line comprises applying about 0 volts to the bit line.

28. The method of claim 25, wherein applying the voltage to the bit line comprises applying an inhibit voltage to the bit line to prevent programming of the target memory cell.

29. The method of claim 25 further comprises applying a voltage to a drain select line coupled to a control gate of a drain select gate that selectively couples the bit line to the NAND string that includes the target memory cell, wherein the voltage applied to the drain select line is selectable after fabrication of the memory device.

30. The method of claim 25 further comprises setting a length of a time allowed for a voltage applied to word lines that do not include the target memory cell and a voltage applied to the word line that includes the target memory cell to increase from an initial level to the pass voltage, wherein the length of time is selectable after fabrication of the memory device.

31. The method of claim 25 further comprises setting a length of a time that the programming voltage is applied to the word line that includes the target memory cell, wherein the length of time is selectable after fabrication of the memory device.

32. The method of claim 25 further comprises applying Vss to a source select line coupled to a control gate of a source select gate that selectively couples a source line to the NAND string of memory cells that includes the target memory cell.

33. The method of claim 25 further comprises applying Vcc to a source line selectively coupled to the NAND string of memory cells that includes the target memory cell by a source select gate.

34. A method of programming a target memory cell of a memory device, comprising:

applying a first voltage, at a first time, to a word line that includes the target memory cell;

applying a second voltage, at the first time, to word lines that do not include the target memory cell;

applying a third voltage, at the first time, to a bit line selectively coupled to a string of memory cells that includes the target memory cell;

increasing the first and second voltages at substantially the same rate, starting at a second time after the first time, until the first and second voltages reach a pass voltage level at a third time after the second time;

increasing the first voltage from the pass voltage, starting at the third time, to an initial programming voltage level at a fourth time after the third time;

maintaining the first voltage at the initial programming voltage level until a fifth time after the fourth time; and

determining whether the target memory cell is programmed after the fifth time; and

increasing the initial programming voltage level by a step voltage if it is determined that the target memory cell is not programmed;

wherein the initial programming voltage, the step voltage, the pass voltage, a length of time between the second and third times, and a length of time between the third and fifth times are each selectable after fabrication of the memory device.

35. The method of claim 34 further comprises maintaining a fourth voltage applied to a source select line coupled to a control gate of a source select gate that selectively couples a source line to the string of memory cells that includes the target memory cell at Vss from the first time until after the fifth time.

36. The method of claim 35 further comprises increasing a fifth voltage applied to the source line from about 0 volts, starting at the first time, to Vcc at the second time and maintaining the fifth voltage at Vcc from the second time until after the fifth time.

37. The method of claim 36 further comprises increasing a sixth voltage applied to a drain select line coupled to a control gate of a drain select gate that selectively couples the bit line to the NAND string that includes the target memory cell from about zero volts, starting at the first time, to Vcc before the second time, decreasing the fifth voltage from Vcc to a third voltage level, at the second time, that is selectable after fabrication of the memory device, and maintaining the sixth voltage at the third voltage level from the second time until after the fifth time.

38. The method of claim 34 further comprising decreasing the first and second voltages to about 0 volts after the fifth time, but before determining whether the target memory cell is programmed.

39. The method of claim 34, wherein applying the third voltage, at the first time, to a bit line further comprises maintaining the third voltage at about 0 volts from the first time until after the fifth time or increasing the third voltage from about 0 volts, starting at the first time, to an inhibit voltage at the second time and maintaining the third voltage at the inhibit voltage from the second time until after the fifth time.

40. A method of programming a memory device, comprising:

applying a first voltage, at a first time, to a first word line that includes a plurality of memory cells to be programmed;

applying a second voltage, at the first time, to second word lines that include memory cells not to be programmed;

applying a third voltage, at the first time, to one or more first bit lines selectively coupled to the first word line and the second word lines for programming one or more first memory cells, of the plurality of memory cells of the first word line to be programmed, at a first logic level;

applying a fourth voltage, at the first time, to one or more second bit lines selectively coupled to the first word line and the second word lines for programming one or more second memory cells, of the plurality of memory cells of the first word line to be programmed, at a second logic level;

increasing the first and second voltages at substantially the same rate, starting at a second time after the first time, until the first and second voltages reach a pass voltage level at a third time after the second time;

increasing the first voltage from the pass voltage, starting at the third time, to an initial programming voltage level at a fourth time after the third time;

maintaining the first voltage at the initial programming voltage level until a fifth time after the fourth time; and

determining whether the one or more first memory cells are programmed at the first logic level after the fifth time; and

increasing the initial programming voltage level by a step voltage if it is determined that the one or more first memory cells are not programmed at the first logic level;

wherein the initial programming voltage, the step voltage, the pass voltage, a length of time between the second and third times, and a length of time between the third and fifth times are each selectable after fabrication of the memory device.

41. The method of claim 40 further comprises maintaining a fifth voltage applied to a source select line, coupled to control gates of source select gates of the memory device, at Vss from the first time until after the fifth time, wherein each source select gate selectively couples a corresponding string of memory cells that includes one of memory cells to be programmed to a common source line.

42. The method of claim 41 further comprises increasing a sixth voltage applied to the common source line from about 0 volts, starting at the first time, to Vcc at the second time and maintaining the fifth voltage at Vcc from the second time until after the fifth time.

43. The method of claim 42 further comprises increasing a seventh voltage applied to a drain select line, coupled to control gates of drain select gates of the memory device, from about zero volts, starting at the first time, to Vcc before the second time, decreasing the seventh voltage from Vcc to a third voltage level, at the second time, that is selectable after fabrication of the memory device, and maintaining the seventh voltage at the third voltage level from the second time until after the fifth time, wherein each drain select gate selectively couples a corresponding string of memory cells that includes one of memory cells to be programmed to one of the first or second bit lines.

44. The method of claim 40 further comprising decreasing the first and second voltages to about 0 volts after the fifth time, but before determining whether the one or more first memory cells are programmed at the first logic level.

45. The method of claim 40, wherein applying a third voltage, at the first time, to one or more first bit lines further comprises maintaining the third voltage at about 0 volts from the first time until after the fifth time.

46. The method of claim 45, wherein applying a fourth voltage, at the first time, to one or more second bit lines further comprises increasing the fourth voltage from about 0 volts, starting at the first time, to an inhibit voltage at the second time and maintaining the fourth voltage at the inhibit voltage from the second time until after the fifth time.

47. A memory device, comprising:

an array of memory cells;

a first register for storing a value corresponding to an initial programming voltage;

a second register for storing a value corresponding to a voltage step; and

control circuitry coupled to the array of memory cells and the first and second registers;

wherein the control circuitry is adapted to iteratively apply a programming voltage to a control gate of a target memory cell during programming of the target memory cell;

wherein the control circuitry is adapted to apply a programming voltage substantially equal to the initial programming voltage on a first iteration;

wherein the control circuitry is adapted to increase the programming voltage by an amount substantially equal to the voltage step during successive iterations; and

wherein the first and second registers are programmable after fabrication.

48. The memory device of claim 47, wherein the first and second registers are two-bit registers.

49. The memory device of claim 47, wherein the control circuitry is adapted to apply a pass voltage to control gates of non-target memory cells.

50. The memory device of claim 49 further comprises a third register coupled to the control circuitry for storing a value corresponding to the pass voltage.

51. The memory device of claim 50, wherein the third register is programmable after fabrication.

52. The memory device of claim 50, wherein the third register is a two-bit register.

53. The memory device of claim 49, wherein the control circuitry is adapted to set a length of a time allowed for a voltage applied to the control gates of non-target memory cells and a voltage applied to the control gate of the target memory cell to increase from an initial level to the pass voltage.

54. The memory device of claim 53 further comprises a third register coupled to the control circuitry for storing a value corresponding to the length of time allowed for a voltage applied to the control gates of non-target memory cells and a voltage applied to the control gate of the target memory cell to increase from an initial level to the pass voltage.

55. The memory device of claim 54, wherein the third register is a two-bit register.

56. The memory device of claim 47, wherein the control circuitry is adapted to set a length of the time interval during which the programming voltage is applied to the control gate of the target memory cell.

57. The memory device of claim 56 further comprises a third register coupled to the control circuitry for storing a value corresponding to the length of a time interval during which the programming voltage is applied to the control gate of the target memory cell.

58. A NAND memory device comprising:

a memory array comprising;

a plurality of rows of memory cells, each row connected to a word line; and

a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a drain select gate of the respective column and to a source line through a source select gate of the respective column;

control circuitry coupled to the memory array, the control circuitry adapted to perform a method for programming a target memory cell of the memory array, comprising;

applying a first voltage, at a first time, to a word line that includes the target memory cell;

applying a second voltage, at the first time, to word lines that do not include the target memory cell;

increasing the first and second voltages at substantially the same rate, starting at a second time after the first time, until the first and second voltages reach a pass voltage level at a third time after the second time;

increasing the first voltage from the pass voltage, starting at the third time, to an initial programming voltage level at a fourth time after the third time;

maintaining the first voltage at the initial programming voltage level until a fifth time after the fourth time;

determining whether the target memory cell is programmed after the fifth time; and

increasing the initial programming voltage level by a step voltage if it is determined that the target memory cell is not programmed;

a first register for storing a value corresponding to the pass voltage level, the first register programmable after fabrication and coupled to the control circuitry;

a second register for storing a value corresponding to the initial programming level, the second register programmable after fabrication and coupled to the control circuitry;

a third register for storing a value corresponding to the voltage step, the third register programmable after fabrication and coupled to the control circuitry;

a fourth register for storing a value corresponding to the length of time between the second and third times, the fourth register programmable after fabrication and coupled to the control circuitry; and

a fifth register for storing a value corresponding to a length of time between the third and fifth times, the fifth register programmable after fabrication and coupled to the control circuitry.

59. The NAND memory device of claim 58, wherein the method further comprises maintaining a third voltage applied to a source select line coupled to a control gate of a source select gate that selectively couples a source line to a NAND string of memory cells that includes the target memory cell at Vss from the first time until after the fifth time.

60. The NAND memory device of claim 59, wherein the method further comprises maintaining a fourth voltage applied to a bit line selectively coupled to the NAND string of memory cells that includes the selected memory cell at about 0 volts from the first time until after the fifth time or increasing the fourth voltage from about 0 volts, starting at the first time, to an inhibit voltage at the second time and maintaining the fourth voltage at the inhibit voltage from the second time until after the fifth time.

61. The NAND memory device of claim 60, wherein method further comprises increasing a fifth voltage applied to the source line from about 0 volts, starting at the first time, to Vcc at the second time and maintaining the fifth voltage at Vcc from the second time until after the fifth time.

62. The NAND memory device of claim 61, wherein the method further comprises increasing a sixth voltage applied to a drain select line coupled to a control gate of a drain select gate that selectively couples the bit line to the NAND string that includes the target memory cell from about zero volts, starting at the first time, to Vcc before the second time, decreasing the sixth voltage from Vcc to a third voltage level at the second time, and maintaining the sixth voltage at the third voltage level from the second time until after the fifth time.

63. The NAND memory device of claim 62 further comprises a sixth register for storing a value corresponding to the third voltage level, the sixth register programmable after fabrication and coupled to the control circuitry.

64. The NAND memory device of claim 58, wherein the method further comprises decreasing the first and second voltages to about 0 volts after the fifth time, but before determining whether the target memory cell is programmed.