Partial string erase scheme in a flash memory device

• US 20060256623A1
• Filed: 05/12/2005
• Published: 11/16/2006
• Est. Priority Date: 05/12/2005
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Application Number:
  US11/127,619
• Publication Number:
  US 20060256623A1
• Time in Patent Office: Days
• US Class Current: 365/185.290
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A memory block has an increased quantity of memory cells while keeping the erase block the same size. The memory block is broken down into at least two memory sub-blocks. While one sub-block is biased with erase voltages, the other sub-block or shadow block is biased with erase inhibit voltages. For wear leveling purposes, the shadow block only experiences a predetermined quantity of program/erase cycles that is less than the maximum experienced by the normal memory sub-block.

Claims

1. A method for erasing a memory device having a memory array comprising a plurality of memory strings coupled to a source line and fabricated on a substrate, the method comprising:

biasing with an erase voltage a first predetermined subset of a first memory string; and

biasing with an erase inhibit voltage a second predetermined subset of the first memory string.

2. The method of claim 1 wherein the memory array is a flash memory array.

3. The method of claim 1 wherein biasing with erase voltages comprises biasing selected word lines with a ground potential.

4. The method of claim 1 wherein biasing with inhibit voltages comprises biasing unselected word lines at a voltage greater than V_CC.

5. The method of claim 3 wherein biasing with erase voltage further comprises biasing the substrate and a source line coupled to the first memory string at a voltage greater than V_CC.

6. The method of claim 1 wherein the first memory string is comprised of 64 memory cells and the first and second predetermined subsets are each comprised of 32 memory cells.

7. The method of claim 1 and further comprising:

comparing a quantity of program/erase cycles performed on the second predetermined subset to a maximum threshold; and

inhibiting an erase operation on the second predetermined subset in response to the comparison.

8. The method of claim 7 wherein the erase operation to the second predetermined subset is inhibited when the quantity of program/erase cycles is greater than the maximum threshold.

9. A method for erasing a memory device having a memory array comprising a plurality of memory cell strings each coupled to a source line and fabricated on a substrate, each memory cell string comprising a first subset of memory cells and a second subset of memory cells, the method comprising:

determining a quantity of program/erase cycles performed on the second subset of memory cells;

preventing further erase operations on the second subset of memory cells if the quantity of program/erase cycles is greater than a predetermined threshold;

biasing the first subset of memory cells with erase voltages; and

biasing the second subset of memory cells with erase inhibit voltages.

10. The method of claim 9 and further including if the quantity of program/erase cycles is less than the predetermined threshold, biasing the first subset of memory cells with erase inhibit voltages and biasing the second subset of memory cells with erase voltages.

11. The method of claim 9 wherein the first and second subsets of memory cells are comprised of an equivalent quantity of memory cells.

12. The method of claim 9 wherein the predetermined threshold is five thousand program/erase cycles.

13. A memory device comprising:

a memory array comprising a plurality of memory cell strings each coupled to a source line and fabricated on a substrate, each memory cell string comprising a first subset of memory cells and a second subset of memory cells; and

memory control circuitry coupled to the memory array, the control circuitry adapted to control program and erase operations of the memory array such that only one of the first or the second subsets of memory cells of each memory cell string is biased for an erase operation at any one time.

14. The device of claim 13 wherein the memory control circuitry is further adapted to inhibit the second subset of memory cells while the first subset is biased for the erase operation.

15. The device of claim 13 wherein the memory control circuitry is further adapted to execute a wear leveling method such that the second subset of memory cells can only experience a predetermined quantity of program/erase cycles that is less than a maximum quantity of program/erase cycles experienced by the first subset of memory cells.

16. The device of claim 14 wherein the memory control circuitry is further adapted to bias unselected word lines of the second subset of memory cells at a voltage that inhibits an erase operation.

17. A memory device comprising:

a memory array comprising a plurality of memory blocks each having a source line and fabricated on a substrate, each memory block comprising a first subset memory block and a second subset memory block; and

memory control circuitry coupled to the memory array, the control circuitry adapted to control program and erase operations of the memory array such that only one of the first subset memory block or the second subset memory block is biased for an erase operation at any one time.

18. The device of claim 17 wherein the memory control circuitry erase inhibits one of the first or the second subset memory block while the remaining first or second subset memory block is being erased.

19. The device of claim 17 wherein the first subset memory block and the second subset memory block are comprised of an equivalent quantity of memory cells.

20. An electronic system comprising:

a processor that generates memory signals; and

a flash memory device, coupled to the processor, that operates in response to the memory signals, the device comprising;

a memory array comprising a plurality of memory cell strings each coupled to a source line and fabricated on a substrate, each memory cell string comprising a first subset of memory cells and a second subset of memory cells; and

memory control circuitry coupled to the memory array, the control circuitry adapted to control program and erase operations of the memory array such that only the first subset of memory cells of each memory cell string is biased for an erase operation.

21. The system of claim 20 wherein the processor is a state machine.

22. The system of claim 20 wherein the flash memory device is a NAND type flash memory device.

23. A method for erasing a memory device having a memory array comprising a plurality of memory cell strings each coupled to a source line and fabricated on a substrate, each memory cell string comprising a first subset of memory cells and a second subset of memory cells, each subset having 32 memory cells, the method comprising:

determining a quantity of program/erase cycles performed on the second subset of memory cells;

preventing further erase operations on the second subset of memory cells if the quantity of program/erase cycles is greater than a predetermined threshold;

biasing selected word lines of the first subset of memory cells at ground potential and the substrate and source line at a voltage greater than V_CC; and

biasing unselected word lines of the second subset of memory cells at a voltage greater than V_CC.

24. The method of claim 23 wherein each memory cell string is comprised of 64 memory cells, a select drain transistor, and a select source transistor coupled to the source line.

25. A method for erasing a memory device having a memory array comprising a plurality of memory strings coupled to a source line and fabricated on a substrate, the method comprising:

biasing the substrate and a source line coupled to a first memory string at a voltage greater than V_CC;

biasing, with an erase voltage, selected word lines of the first memory string; and

floating unselected word lines of the first memory string.

26. The method of claim 25 and further including if one or more of the unselected word lines are not at an erase inhibit voltage, biasing the unselected word lines not at an erase inhibit voltage with an inhibit voltage greater than Vcc.

27. The method of claim 26 wherein the one or more unselected word lines are substantially adjacent to at least one of the selected word lines.

28. The method of claim 25 wherein biasing the substrate and the source line includes biasing the substrate and the source line at 20V.