Method and system for improving integrated circuit manufacturing yield

• US 20060258023A1
• Filed: 05/10/2005
• Published: 11/16/2006
• Est. Priority Date: 05/10/2005
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Gwynn, Brent, Fenrick, Michael, Rolofson, Kirk
• Application Number:
  US11/125,863
• Publication Number:
  US 20060258023A1
• Time in Patent Office: Days
• US Class Current: 438/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A lithographic scanner collects surface height information concurrently with conducting a lithographic scan process. A defect identification module identifies wafers having a surface height metric greater than a determined threshold. The identified wafers may be separated for rework to correct the surface defects such as hotspots and improve manufacturing yield without requiring additional equipment. In one embodiment, the surface height metric is a maximum variation from a moving average surface height. In one embodiment, yield data is correlated with surface height information to determine a threshold value corresponding to defective circuit die.

Claims

1. A method to improve integrated circuit manufacturing yield, the method comprising:

collecting surface height information for a wafer concurrent with conducting a lithographic scan process;

identifying wafers having a surface height metric that is greater than a selected threshold; and

reworking the identified wafers.

2. The method of claim 1, wherein reworking the identified wafers comprises removing at least one interconnection layer.

3. The method of claim 1, further comprising identifying a tool responsible for the surface height variation.

4. The method of claim 1, further comprising selecting the selected threshold based on yield data.

5. The method of claim 1, further comprising routing the identified wafers to a rework station.

6. The method of claim 1, wherein the surface height metric is a variation from a moving average surface height.

7. The method of claim 1, further comprising stepping a wafer to a new scanning position.

8. A system to improve integrated circuit manufacturing yield, the system comprising:

a lithographic scanner configured to collect surface height information for a wafer concurrent with conducting a lithographic scan process;

a defect identification module configured to automatically identify wafers having a surface height metric that is greater than a selected threshold; and

at least one tool configured to rework the identified wafers.

9. The system of claim 9, wherein the at least one tool comprises a tool for removing at least one interconnection layer.

10. The system of claim 9, wherein the defect identification module is further configured to automatically identify a tool responsible for the surface height variation.

11. The system of claim 9, further comprising a controller configured to route the identified wafers to a rework station.

12. The system of claim 9, wherein the surface height metric is a variation from a moving average surface height.

13. The system of claim 9, wherein the lithographic scanner is further configured to step a wafer to a new scanning position.

14. A system to improve integrated circuit manufacturing yield, the system comprising:

means for collecting surface height information for a wafer while concurrently conducting a lithographic scan process;

means for identifying wafers having a surface height metric that is greater than a selected threshold; and

means for reworking the identified wafers.

15. The system of claim 14, wherein the means for reworking the identified wafers comprises means for removing at least one interconnection layer.

16. The system of claim 14, further comprising means for routing the identified wafers to a rework station.

17. The system of claim 14, further comprising means for stepping a wafer to a new scanning position.

18. A machine readable medium comprising operations to improve integrated circuit manufacturing yield, the operations comprising:

collecting surface height information for a wafer while concurrently conducting a lithographic scan process;

identifying wafers having a surface height metric that is greater than a selected threshold; and

reworking the identified wafers.

19. The machine readable medium of claim 18, wherein the operations further comprise identifying a tool responsible for the surface height variation.

20. The machine readable medium of claim 18, wherein the surface height metric is a maximum variation for an entire wafer of a moving average surface height.

21. The machine readable medium of claim 18, wherein the operations further comprise stepping a wafer to a new scanning position.