Method of forming a trench structure having one or more diodes embedded therein adjacent a PN junction

• US 20060258081A1
• Filed: 07/14/2006
• Published: 11/16/2006
• Est. Priority Date: 11/05/2002
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Christopher Boguslaw Kocon, Joseph Andrew Yedinak
• Inventors: Yedinak, Joseph Andrew, Kocon, Christopher Boguslaw
• Granted Patent: US 7,582,519 B2
• Time in Patent Office: Days
• US Class Current: 438/237
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7818 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A semiconductor structure is formed as follows. A semiconductor region is formed to have a P-type region and a N-type region forming a PN junction therebetween. A first trench is formed extending in the semiconductor region adjacent at least one of the P-type and N-type regions is formed. At least one diode is formed in the trench.

Claims

1. A method of forming a semiconductor structure, comprising:

forming a semiconductor region comprising a P-type region and a N-type region forming a PN junction therebetween;

forming a first trench extending in the semiconductor region adjacent at least one of the P-type and N-type regions; and

forming at least one diode in the first trench.

2. The method of claim 1 further comprising:

forming an insulating layer extending along sidewalls of the first trench but being discontinuous along the bottom of the first trench.

3. The method of claim 1 further comprising:

forming an insulating layer configured to insulate the at least one diode from at least one of the P-type and N-type regions along the sidewalls of the first trench.

4. The method of claim 1 wherein the semiconductor region is an epitaxial layer, the method further comprising:

forming the epitaxial layer over and in contact with a substrate, the epitaxial layer being of the same conductivity type as the substrate.

5. The method of claim 4 further comprising:

forming a body region in the epitaxial layer, the body region being one of the P-type and N-type regions and the other one of the P-type and N-type regions forming a drift region,

wherein the at least one diode is arranged in the first trench so that when the semiconductor structure is biased in a blocking state an electric field induced in the at least one diode influences an electric field in the drift region to thereby increase the blocking voltage of the semiconductor structure.

6. The semiconductor structure of claim 4 further comprising:

forming a body region in the epitaxial layer, the body region being one of the P-type and N-type regions and the other one of the P-type and N-type regions forming a drift region,

wherein the at least one diode is arranged in the first trench so that when the semiconductor structure is biased in a blocking state an electric field induced in the at least one diode results in a uniform charge distribution in the drift region.

7. The method of claim 1 wherein the act of forming at least one diode comprises:

forming N-type and P-type regions alternately stacked on top of one another in the first trench.

8. The method of claim 1 wherein the act of forming at least one diode comprises:

forming N-type and P-type regions alternately arranged adjacent one another parallel to a surface of the semiconductor structure.

9. The method of claim 1 wherein the at least one diode is from one of doped silicon material and doped polysilicon material.

10. The method of claim 1 wherein the semiconductor structure is a MOSFET, the method further comprising:

forming a second trench in the semiconductor region, the second trench being laterally spaced from the first trench; and

forming a gate in the second trench.

11. The method of claim 1 wherein the semiconductor structure is a MOSFET, the method further comprising:

forming a planar gate structure along a surface region of the semiconductor region, the gate structure being laterally spaced from the first trench.

12. The method of claim 1 wherein the semiconductor structure is a MOSFET, the method further comprising:

forming a gate in the first trench over but insulated from the at least one diode.

13. The method of claim 1 wherein the semiconductor structure is a MOSFET, the method further comprising:

forming a drain terminal and a source, wherein the at least one diode is electrically connected between the drain and source.

14. The method of claim 1 wherein the semiconductor structure is a MOSFET, the method further comprising:

forming a drain terminal and a source terminal along opposite surfaces of the semiconductor structure, the first trench extending vertically between the drain terminal and the source terminal.

15. The method of claim 14 wherein the act of forming at least one diode comprises:

forming N-type and P-type regions alternately stacked on top of one another in the first trench.

16. The method of claim 1 wherein the semiconductor structure is a MOSFET, the method further comprising:

forming a drain terminal and a source terminal both located along one surface of the semiconductor structure, the first trench extending laterally between the drain terminal and the source terminal.

17. The method of claim 16 wherein the act of forming at least one diode comprises:

forming N-type and P-type regions alternately arranged adjacent one another along the lateral dimension.

18. The method of claim 1 wherein the semiconductor structure is a rectifier, the method comprising:

forming an anode terminal electrically connected to one of the P-type and N-type regions and a cathode terminal electrically connected to the other one of the P-type and N-type regions.

19. The method of claim 18 wherein the anode and cathode terminals are located along opposite surfaces of the rectifier, the first trench extending vertically between the anode and cathode terminals, wherein the act of forming at least one diode comprises:

forming P-type and N-type regions alternately stacked on top of each other in the first trench.

20. The method of claim 1 wherein the first trench is a narrow and deep trench extending vertically between opposite surfaces of the semiconductor structure.

21. The method of claim 1 wherein the first trench is a wide and shallow trench extending laterally parallel to a surface of the semiconductor structure.

22. A method of forming a semiconductor structure, comprising:

forming an epitaxial layer over and in contact with a substrate, the epitaxial layer being of the same conductivity type as the substrate;

forming a body region in the epitaxial layer so that after forming the body region the epitaxial layer comprises a P-type region and an N-type region forming a PN junction therebetween, the body region being one of the P-type and N-type regions, and a drift region being the other one of the P-type and N-type regions, the drift region being of the same conductivity type as the substrate;

forming a plurality of laterally spaced trenches each extending through at least a portion of the drift region; and

forming a plurality of diodes in each of the plurality of trenches.

23. The method of claim 22 wherein the plurality of diodes are formed in each of the plurality of trenches such that an electric field induced in one or more of the plurality of diodes influences an electric field in the drift region such that a blocking voltage of the semiconductor structure is increased.

24. The method of claim 22 further comprising:

forming an insulating layer in each of the plurality of trenches, the insulating layer extending along the trench sidewalls but being discontinuous along the bottom of the trench.

25. The method of claim 22 further comprising:

forming at least two terminals located along opposite surfaces of the semiconductor structure, the plurality of trenches extending vertically between the two terminals,

wherein the act of the forming a plurality of diodes comprises forming P-type and N-type regions alternately stacked on top of each other in each trench.

26. The method of claim 22 further comprising:

forming at least two terminals located along one surface of the semiconductor structure, the plurality of trenches extending laterally between the two terminals,

wherein the act of forming a plurality of diodes comprises forming P-type and N-type regions alternately arranged adjacent one another along the lateral dimension.